p650-05sc PhaseLink Corp., p650-05sc Datasheet - Page 3

• Manufacturer Part Number: p650-05sc
• Description: Low Emi Network Lan Clock
• Manufacturer: PhaseLink Corp.

PLL650-05
Low EMI Network LAN Clock
since the pin also needs to serve as output. In the case of two level input pins, an internal pull-up resistor is present. This allows
a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level
input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-directional pin to a non-default value, the
input must be connected to GND or VDD through an external pull-down/pull-up resistor. Note: when the output load presents a
low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up
to a logical “one”, and an external pull-up resistor may be required.
For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the
internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the
pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is
recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application
Diagram). Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this
resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may
have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is
particularly true when driving 74FXX TTL components.
APPLICATION DIAGRAM
Internal to chip
External Circuitry
VDD
R
up
R
Power Up
Reset
RB
Clock Load
Bi-directional pin
Output
EN
/
R
4
Latched
UP
Latch
Input
Jumper options
NOTE: Rup=120kΩ for 50MHz_OE (Pin2); Rup=60k Ω for FS(0:1). R starts from 1 to 0 while RB starts from 0 to 1.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 3