p650-03scl PhaseLink Corp., p650-03scl Datasheet

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p650-03scl

Manufacturer Part Number
p650-03scl
Description
Low Emi Network Lan Clock
Manufacturer
PhaseLink Corp.
Datasheet
FEATURES
DESCRIPTION
The PLL 650-03 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25.0 MHz crystal, and produces multiple output
clocks for networking chips, PCI devices, SDRAM, and
ASICs.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/16/06 Page 1
Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
4 outputs fixed at 50MHz with output disable, 1 output
selectable at 25MHz or 100MHz with output disable
SDRAM selectable frequencies of 66.6, 75, 83.3, 100MHz
(Double Drive Strength).
Spread spectrum technology selectable for EMI
reduction from ±0.5%, ±0.75% center for SDRAM and
CPU.
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
Available in 16-Pin 150mil SOIC
XOUT
FS (0:3)
XIN
XTAL
OSC
GREEN
Control
Logic
package
.
PIN CONFIGURATION
FREQUENCY TABLE
FS0
XOUT/50MHz_OE*^
0
0
1
1
Note: SDRAMx2: Double Drive strength.
resistor *: Bi-directional pin (input value is latched upon power-up).
Low EMI Network LAN Clock
50MHz/FS0*^
50MHz/FS1*^
50MHz/FS2*
4
1
1
FS1
1
0
0
1
GND
GND
VDD
XIN
83.3MHz
66.6MHz
100MHz
T
75MHz
SDRAM
50MHz
(can be disabled)
25MHz/100 MHz
(can be disabled)
SDRAM (66.6, 75, 83.3, 100MHz)
1
2
3
4
5
6
7
8
SST
SST
SST
SST
PLL650-03
T
SST: SST modulation applied
: Tri-Level input ^: Internal pull-up
FS2
M
0
1
16
15
14
13
12
11
10
9
100MHz
VDD
25MHz/100MHz
GND
GND
50MHz/SS0*
VDD
SDRAMx2
VDD
Disable
Pin 14
25MHz
SST
T

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p650-03scl Summary of contents

Page 1

FEATURES • Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. • Advanced, low power, sub-micron CMOS processes. • 25MHz fundamental crystal or clock input. • 4 outputs fixed at 50MHz with output disable, ...

Page 2

PIN DESCRIPTIONS Name Number XIN 1 XOUT/50MHz_OE 2 50MHz/FS(0:2) 5,7,8 50MHz/SS0 9 SDRAMx2 11 25MHz/100MHz 14 VDD 4,10,15,16 GND 3,6,12,13 SPREAD SPECTRUM SELECTION TABLE SS0 FUNCTIONAL DESCRIPTION Selectable spread spectrum and output frequencies The PLL650-03 provides selectable ...

Page 3

Connecting a bi-directional pin A bi-directional pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the ...

Page 4

Electrical Specifications 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model Exposure of the device under conditions beyond the limits ...

Page 5

DC Specifications PARAMETERS SYMBOL Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Operating Supply Current ...

Page 6

... A1 .050 e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL650- Marking P650-03SC P650-03SC P650-03SCL P650-03SCL PLL650-03 Low EMI Network LAN Clock NONE= TUBE R=TAPE AND REEL NONE=NORMAL PACKAGE L=GREEN PACKAGE ...

Page 7

LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax ...

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