p650-05sc PhaseLink Corp., p650-05sc Datasheet

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p650-05sc

Manufacturer Part Number
p650-05sc
Description
Low Emi Network Lan Clock
Manufacturer
PhaseLink Corp.
Datasheet
FEATURES
DESCRIPTION
The PLL650-05 is a low cost, low jitter, high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, this
device can produce multiple clock outputs from a 25.0MHz
crystal or reference clock. This makes the PLL650-05 an
excellent choice for systems requiring clocking for network
chips, PCI devices, SDRAM, and ASICs.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
3 fixed outputs of 25MHz, 75Mhz and 125Mhz with
output disable
SDRAM selectable frequencies of 105, 83.3, 140MHz
(Double Drive Strength).
Spread spectrum technology selectable for EMI
reduction from ±0.5%, ±0.75% center for SDRAM and
CPU.
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
Available in 16-Pin 150mil SOIC
XOUT
FS (0:1)
XIN
XTAL
OSC
.
Control
Logic
PIN CONFIGURATION
FREQUENCY TABLE
XOUT/ENB_125M*^
FS1
Note: SDRAMx2: Double Drive strength.
resistor *: Bi-directional pin (input value is latched upon power-up).
0
0
1
1
Low EMI Network LAN Clock
ENB_75MHz^
75MHz/FS1*^
1
1
1
1
125MHz
FS0
0
1
0
1
GND
GND
VDD
XIN
SDRAM (105, 83.3, 140MHz)
75 MHz
(can be disabled)
25MHz
125MHz
(can be disabled)
1
2
3
4
5
6
7
8
PLL650-05
SDRAMX2
140MHz
83.3MHz
105MHz
T
Tristate
: Tri-Level input ^: Internal pull-up
16
15
14
13
12
11
10
9
SST
SST
SST
VDD
25MHz/FS0*^
GND
GND
SS0
VDD
SDRAMx2
VDD
T

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p650-05sc Summary of contents

Page 1

FEATURES • Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. • Advanced, low power, sub-micron CMOS processes. • 25MHz fundamental crystal or clock input. • 3 fixed outputs of 25MHz, 75Mhz and 125Mhz ...

Page 2

PIN DESCRIPTIONS Name Number XIN 1 XOUT/ENB_125M 2 125MHz 5 75MHz/FS1 7 ENB_75M 8 SS0 9 SDRAMx2 11 25MHz/FS0 14 VDD 4,10,15,16 GND 3,6,12,13 SPREAD SPECTRUM SELECTION TABLE SS0 FUNCTIONAL DESCRIPTION Selectable spread spectrum and output frequencies ...

Page 3

In the case of two level input pins, an internal pull-up resistor is present. This allows a default value to be set when no external pull down resistor is connected between ...

Page 4

Electrical Specifications 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model Exposure of the device under conditions beyond the limits ...

Page 5

DC Specification PARAMETERS SYMBOL Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Operating Supply Current ...

Page 6

... A1 1.27 BSC e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL650- Marking P650-05SC P650-05SC PLL650-05 Low EMI Network LAN Clock TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE S=SOIC Package Option SOIC - Tape and Reel ...

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