mcs1000 MosChip, mcs1000 Datasheet - Page 22
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mcs1000
Manufacturer Part Number
mcs1000
Description
Security Processor
Manufacturer
MosChip
Datasheet
1.MCS1000.pdf
(30 pages)
Page 22
MCS1000
Security Processor
General Interface Blocks
The General Interface Blocks consist of three Ethernet controllers, PCI interface, Memory Controller (SDRAM,
Flash and Local-bus), serial port, GPIO and Clock Interface. These blocks are described briefly in this section.
For a detailed description see the next section.
Ethernet Interface
The MCS1000 has three (3) Fast Ethernet controllers. These controllers consist of a MAC and a PHY. Only the
PHY interfaces are brought off-chip. The PHYs can be connected directly to Ethernet magnetics.
The Ethernet interfaces consist of DMA, TLI, MAC, and PHY sub-blocks. The DMA automates memory transfers
and frees the CPU from this task. The Transaction Layer Interface (TLI) is a 32-bit wide block designed to
provide a bridge between the DMA controller and a 10/100 Ethernet MAC. The TLI uses two (2) 2 KByte FIFOs
for receive and transmit buffering.
The MCS1000 has an alternate Ethernet configuration. In this configuration the third Ethernet interface
(Ethernet-C) does not use the internal PHY, and its MII is available on the external pins. In this configuration
LED signals for Ethernet-A and B, eight (8) GPIO and three (3) UART control signals are all unavailable. This
configuration is controlled via pull-ups and pull-downs on the four (4) configuration pins and cannot be entered
through software.
Ethernet MAC Features
The MAC core has the following features:
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IEEE 802.3, 802.3u specification compliant
Supports 10/100 Mbps data transfer rates
VLAN support
Full-duplex and half-duplex support
Supports flow-control frames in full-duplex
mode
Collision detection and auto retransmission
on collisions in half-duplex mode
CSMA/CD protocol support for half-duplex
mode
Preamble generation and removal
Automatic 32-bit CRC generation and
checking
Options to insert PAD/CRC32 on transmit
Insertion and stripping of padding Bytes
Flexible address filtering modes:
Promiscuous mode
Pass all incoming packets with a status
report
Separate 32-bit status is returned for transmit
and receive packets
o One 48-bit perfect address
o 64 hash-filtered multicast addresses
o Pass all multicast addresses
Ethernet PHY Features
There are three (3) integrated physical layers (PHYs),
one connected to each internal MAC.
are designed to be connected directly to Ethernet
magnetics.
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10/100BASE-TX Ethernet PHY device
Data is reliable over cable lengths up to 100
meters
Supports transformers with 1.41:1 turns ratio
(E.g.: Tyco 1605011-1)
Wave-shaping – no external filter required
Full and half-duplex operation with full-
featured Auto-Negotiation function
LED indicators (3 each): Fully configurable
for Link, TX activity, RX activity, Collision, 10
Mbps, 100 Mbps, Full or Half Duplex
Media Dependent Interface / Media
Dependent Interface Crossover MDI/MDIX
Built-in Loop-Back and Test Modes
The PHYs
Rev.
1.1