mcs1000 MosChip, mcs1000 Datasheet - Page 14

• Manufacturer Part Number: mcs1000
• Description: Security Processor
• Manufacturer: MosChip

Page 14
MCS1000
Security Processor
Hardware Description
The red and blue busses are the configuration buses. The write data and address busses (red) go to all
devices. The return data bus (blue) is gathered into the Configuration Block where it is multiplexed according
to the address. The green and violet are the data busses. The bus (black) going from the lower AHB2VCI64
to the Memory Controller is the Control/Address for the memory controller. All internal data busses are 64-
bit@50MHz. The SDRAM back-end is translated from a 64-bit@50MHz to a 32-bit@100MHz interface.
All blocks inside the IPSec Unit (cryptography, authentication and I/O) run at 50MHz except for the four (4)
3DES cryptography blocks which run at 100MHz.
There are two (2) PLLs in the PLL Block. One PLL is for the CPU core and the other is for the Hardware IPSec
Module and the remaining blocks. Both of the PLLs are sourced from the 25 MHz clock taken from the PHYs.
GPIO and
EEPROM
Serial
J T AG
PCI
Port
Controller
UART
PCI
CPU Subsystem
Configuration
ARM926EJ-S
Block
Core
Clock
PLL
AHB2VCI64
AHB2VCI64
Hardware
MAC/
PHY 1
IPSec
Ethernet
1
IPSec Unit
Module
PHY 2
MAC/
Ethernet
2
PHY 3
MAC/
Ethernet
General Interface Blocks
3
Ethernet
Block
DMA
LUP
Packet
Cache
Internal
ROM
I/O Pads
Controller
Memory
Rev.
SDRAM
ADC
- - -
1.1