mcf51em256 Freescale Semiconductor, Inc, mcf51em256 Datasheet - Page 7

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mcf51em256

Manufacturer Part Number
mcf51em256
Description
Microcontrollers Covers Mcf51em256 Mcf51em128
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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1.3.1
Freescale Semiconductor
SCI1, SCI2, SCI3(serial communications
interfaces)
SIM (system integration unit)
SPI1 (FIFO), SPI2, SPI3 (serial peripheral
interfaces)
TPM (Timer/PWM Module)
VREG (voltage regulator)
XOSC1 and XOSC2 (crystal oscillators)
32-bit ColdFire V1 central processor unit (CPU)
— Up to 50.33 MHz ColdFire CPU from 3.6 V to 2.5 V and 20 MHz CPU at 3.6 V to 1.8 V across
— ColdFire instruction set revision C (ISA_C) plus MAC
— 32-bit multiply and accumulate (MAC) optimized for 16×16±32 operations; supports signed or
On-chip memory
— MCF51EM256/128 series support two independent flash arrays; read/program/erase over full
— Random-access memory (RAM)
— Security circuitry to prevent unathorized access to RAM and Flash contents
Power-saving modes
— Two ultra-low power stop modes
— New low-power run and low-power wait modes
— Reduced power wait mode
— Peripheral clock enable register can disable clocks to unused modules, thereby reducing
— Ultra-low power independent real time clock with calendar features (IRTC); runs in all MCU
— Ultra-low power external oscillator that can be used in stop modes to provide accurate clock
temperature range of –40 °C to 85 °C
unsigned integer or signed fractional inputs
operating voltage and temperature; allows interrupt processing while programming for robust
program updates
currents
modes; external clock source with trim capabilities; independent voltage source runs IRTC
when MCU is powered-down; tamper detection and indicator; battery monitor output to ADC;
unaffected by MCU resets
source to IRTC, ICS and LCD
Feature List
Unit
Table 2. MCF51EM256 Series Functional Units (continued)
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.3
Preliminary—Subject to Change Without Notice
Serial communications UARTs capable of supporting RS-232 and LIN
protocols
SPI1 has full-complementary drive outputs. SPI2 may be configured
with full-complementary drive output via LCD control registers. SPI3
has open drain outputs on SCLK and (MISO or MOSI). These coupled
with off-chip pull-up resistors, allow interface to an external 5 V SPI.
Timer/PWM module can be used for a variety of generic timer
operations as well as pulse-width modulation
Controls power management across the device
These devices incorporate redundant crystal oscillators in separate
power domains.One is intended primarily for use by the IRTC, and the
other by the CPU and other peripherals.
Function
MCF51EM256 Series Configurations
7

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