mcf5208 Freescale Semiconductor, Inc, mcf5208 Datasheet - Page 32

• Manufacturer Part Number: mcf5208
• Description: Mcf5208 Coldfire Microprocessor Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

NOTES:
1
2
3
4
5
6
DD10
DD11
DD12
DD13
DD14
DD15
Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and
voltage variations.
Num
Electrical Characteristics
5.8.2
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to
properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte
lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early
board design. Please contact your local Freescale representative if questions develop.
The frequency of operation is 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same
frequency as the internal bus clock.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid
for each subsequent DQS edge.
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
32
—
Frequency of Operation
Clock Period (SD_CLK)
Pulse Width High
Pulse Width Low
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
Write Command to first DQS Latching Transition
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
Input Data Skew Relative to DQS (Input Setup)
Input Data Hold Relative to DQS.
DQS falling edge from SDCLK rising (output hold time)
DQS input read preamble width (t
DQS input read postamble width (t
DQS output write preamble width (t
DQS output write postamble width (t
DDR SDRAM AC Timing Characteristics
Characteristic
MCF5208 ColdFire
Table 13. DDR Timing Specifications
RPRE
RPST
WPRE
WPST
)
)
)
)
®
Microprocessor Data Sheet, Rev. 1
t
t
t
t
t
t
Symbol
SDCHACV
DQLSDCH
t
t
SDCHACI
CMDVDQ
t
DQWPRE
DQWPST
t
DQRPRE
t
t
DQRPST
DQDMV
t
DDCKH
t
DDCKL
DQDMI
t
DDCK
DVDQ
DIDQ
—
0.25 × SD_CLK
+ 0.5ns
TBD
0.45
0.45
0.25
Min
2.0
1.5
1.0
0.5
0.9
0.4
0.4
12
—
—
0.5 × SD_CLK
83.33
+ 1.0
Max
TBD
0.55
0.55
1.25
1.1
0.6
0.6
—
—
—
—
—
—
1
Freescale Semiconductor
SD_CLK
SD_CLK
SD_CLK
SD_CLK
SD_CLK
SD_CLK
SD_CLK
Unit
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
—
—
—
—
—
—
—
1
2
3
3
4
5
6
7
8
9