mcf5208 Freescale Semiconductor, Inc, mcf5208 Datasheet - Page 30

• Manufacturer Part Number: mcf5208
• Description: Mcf5208 Coldfire Microprocessor Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

NOTES:
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Electrical Characteristics
Symbol
30
The device supports the same frequency of operation for FlexBus and SDRAM as that of the internal bus clock. Please see the
PLL chapter of the MCF5208 Reference Manual for more information on setting the SDRAM clock rate.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from
this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
Because a read cycle in SDR mode continues using the DQS circuit within the device, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec
is provided as guidance.
SD10
SD11
SD12
SD13
SD1
SD3
SD4
SD5
SD6
SD7
SD8
SD9
Frequency of Operation
Clock Period (t
Pulse Width High (t
Pulse Width Low (t
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_BA, SD_CS[1:0] - Output Valid (t
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_BA, SD_CS[1:0] - Output Hold (t
SD_SDR_DQS Output Valid (t
SD_DQS[3:2] input setup relative to SD_CLK (t
SD_DQS[3:2] input hold relative to SD_CLK (t
Data (D[31:0]) Input Setup relative to SD_CLK
(reference only) (t
Data Input Hold relative to SD_CLK (reference only)
(t
Data (D[31:0]) and Data Mask(SD_DQM[3:0])
Output Valid (t
Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output
Hold (t
DIH
)
DH
)
DV
CK
)
)
DIS
CKL
Characteristic
CKH
)
)
MCF5208 ColdFire
)
DQSOV
Table 12. SDR Timing Specifications
)
CMV
CMH
)
)
®
Microprocessor Data Sheet, Rev. 1
DQSIH
DQSIS
) t
) t
t
t
t
t
DQVSDCH
SDCHDMV
Symbol
SDCHACV
t
SDCHDMI
DQISDCH
t
SDCHACI
t
t
t
DVSDCH
DISDCH
DQSOV
t
SDCKH
SDCKL
SDCK
0.25 × SD_CLK 0.40 × SD_CLK
0.25 × SD_CLK
Does not apply. 0.5 SD_CLK fixed width.
TBD
0.45
0.45
Min
2.0
1.0
1.5
12
—
—
—
0.75 × SD_CLK
0.5 × SD_CLK
Self timed
83.33
+ 1.0
+ 0.5
TBD
Max
0.55
0.55
—
—
—
—
Freescale Semiconductor
SD_CLK
SD_CLK
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
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