mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 265

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
12.2.1.4 Endpoint Controllers
The MCF5272 has eight independent endpoint controllers that manage data transfer
between the on-chip CPU and the USB host for each endpoint. These controllers provide
event notification to the user and manage the IN and OUT FIFO dual-port RAM buffers.
The USB endpoint configuration registers (USBEPOCFGn or USBEPICFGn) are used to
configure each endpoint to support either control, interrupt, bulk, or isochronous transfers.
USB always uses endpoint 0 as a control pipe, so it must be configured for control transfer
mode. Additional control pipes can be provided by other endpoints.
A total of 1024 bytes of dual-port RAM are available for transmit and receive FIFO buffers.
This RAM is partitioned to provide 512 bytes for each direction. The user is responsible for
configuring the FIFO for each endpoint. This configuration is flexible within the following
constraints:
For example, an endpoint with a maximum packet size of 32 bytes can have a FIFO size of
64, 128, or 256 bytes and a starting address of 0, 64, 128, 192, 256, etc.
12.2.1.5 USB Request Processor
The MCF5272 USB request processor automatically processes all of the USB standard
requests listed in Table 12-1 except for
request. The
• For received data:
• For error detection:
• FIFO size must be an integral power of 2
• FIFO size must be at least twice the maximum packet size
• FIFO starting address must be aligned on a boundary defined by the FIFO size.
— NRZI encoding
— Bit stuffing
— Sync detection
— Packet identification
— End-of-packet detection
— Serial-to-parallel conversion
— CRC validation
— NRZI decoding
— Bit unstuffing
— Bad CRC
— Timeout waiting for end-of-packet
— Bit stuffing violations
SYNC
_
FRAME
Chapter 12. Universal Serial Bus (USB)
request is passed to the user as a vendor-specific request. The
SYNC
_
FRAME
and the optional
SET
Module Operation
_
DESCRIPTOR
12-5