mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 241

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
11.5.7 MII Management Frame Register (MMFR)
The MMFR register, Figure 11-10, is used to communicate with the attached MII
compatible PHY device(s), providing read/write access to their MII registers. Performing
a write to the MMFR register causes a management frame to be sourced, unless the MSCR
register has been programmed to 0. In the case of writing to MMFR when MSCR = 0, if the
MSCR register is then written to a non-zero value, an MII frame is generated with the data
previously written to MMFR. This allows MMFR and MSCR to be programmed in either
order if MSCR is currently zero.
Table 11-13 describes the MMFR fields.
To perform a read or write operation on the MII management interface, the MMFR register
is written by the user. To generate a valid read or write management frame, the ST field must
be written with a 01 pattern, the OP field must be written with a 01 (management register
write frame) or 10 (management register read frame), and the TA field must be written with
a 10. If other patterns are written to these fields, a frame is generated but will not comply
with the IEEE 802.3 MII definition. OP field = 1x produces a read-frame operation, while
OP = 0x produces a write-frame operation.
Reset
Reset
31–30
29–28
27–23
22–18
17–16
15–0
Field
Field
Bits
Addr
R/W
R/W
31
15
Name
DATA
ST
OP
ST
RA
PA
TA
30
Figure 11-10. MII Management Frame Register (MMFR)
Start of frame delimiter. Must be programmed to 01 for a valid MII management frame
Operation code. This field must be programmed to 10 (read) or 01(write) to generate a valid
MII management frame. A value of 11 produces a read frame operation while a value of 00
produces a write frame operation, but these frames are not MII-compliant.
PHY address. Specifies one of up to 32 attached PHY devices
Register address. Specifies one of up to 32 registers within the specified PHY device
Turn around. Must be programmed to 10 to generate a valid MII management frame.
Management frame data. Field for data to be written to or read from PHY register
29
OP
28
Table 11-13. MMFR Field Descriptions
27
Chapter 11. Ethernet Module
PA
MBAR + 0x880
Read/Write
Read/Write
Undefined
Undefined
23
DATA
Description
22
RA
Programming Model
18
17
TA
11-17
16
0