st52t430 STMicroelectronics, st52t430 Datasheet - Page 66

• Manufacturer Part Number: st52t430
• Description: 8-bit Intelligent Controller Unit Icu Three Timer/pwms, Adc, Sci
• Manufacturer: STMicroelectronics

A frame error can occur if the parity check hasn’t
been successfully achieved or if the STOP bit
hasn’t been detected.
If the
consecutive bits at logic level 0, a break error
occurs and an interrupt routine request starts.
SCDR_RX Block
It is a finite state machine synchronized with the
clock master signal, CKM.
The SCDR_RX block waits for the signal of
complete reception from the Recovery Buffer, in
order to load the word received. Moreover, the
SCDR_RX block loads the values of FRERR and
NSERR flag bits (Input Register 19), and sets the
RXF flag to 1.
Data is transferred to RAM and the RXF flag is
reset to 0 by using the LDRI instruction in order to
indicate that the SCDR_RX block is empty.
If new data arrives before the previous one has
been transferred to Register File, an overrun error
occurs and OVERR flag of Input Register 19 is set
to 1.
11.2 SCI Transmitter Block
The SCI Transmitter Block consists of the following
blocks:
synchronized, respectively, with the clock master
signal (CKM) and the CLOCK_TX.
The whole block receives the settings for the
following transmission modes (see Table 11.1)
through Configuration Register 20 (M bits):
In case of 9 bit frame transmission, the most
significative
Configuration Register 20.
Instead, in an 8-bit transmission T8 is used to
configure SCI according to information contained
in M (see Table 11.1). In particular, it is used to
choose the polarity control (even or odds) in order
to implement the parity check.
After a RESET signal RST, the SCDR_TX block is
in IDLE state until it receives the enabling signal
TE=1, of Configuration Register 20.
Data is loaded on the peripheral register (OR 9) by
using the instruction LPPR or LDPE. If TE=1 the
data to be transmitted is transferred from DR_TX
block and flag of Input Register 19. TXEM is reset
to 0 in order to indicate that the SCDR_TX block is
full.
66/88
8-bit word and a single stop signal
8-bit word plus a parity bit and a single stop
signal
8-bit word plus a double stop signal
9-bit word
Recovery Buffer Block receives 10
SCDR_TX
bit arrives
and
through
SHIFT
T8
REGISTER,
of
the
Table 11.2 Configuration Register 19 Setting
Bit
0
1
2
3
4
5
6
7
RDRF
Name
ECKF
TDRE
OVR
TXC
BRK
Value
00
01
10
11
0
1
0
1
0
1
0
1
0
1
-
Register Full Interrupt
Register Full Interrupt
Data Register Empty
Data Register Empty
SCI Received Data
SCI Received Data
SCI Overrun Error
SCI Overrun Error
Interrupt Disabled
SCI Transmission
Interrupt Disabled
SCI Transmission
Interrupt Disabled
Interrupt Disabled
Interrupt Enabled
Interrupt Enabled
Interrupt Enabled
Interrupt Enabled
SCI Break Error
SCI Break Error
Transmission
Transmission
Description
Not used
Disabled
SCI End
SCI End
Enabled
10 MHz
20 MHz
5 MHz
5 MHz