st52f510 STMicroelectronics, st52f510 Datasheet - Page 94

• Manufacturer Part Number: st52f510
• Description: 8-bit Intelligent Controller Unit Icu Two Timer/pwms, Adc, I2c, Spi, Sci
• Manufacturer: STMicroelectronics

ST52F510/F513/F514
Bit 7: EVF Event Flag
Bit 6: ADD10 10 bit addressing in Master Mode
Bit 5: TRA Transmitter/Receiver
Bit 4: BUSY Bus busy
94/106
This bit is set by hardware as soon as an
event occurs. It is cleared by software
reading I2C_SR2 register in case of error
event or as described in Figure 14.3. It is also
cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
This bit is set by hardware when the master
has sent the first byte in 10-bit address mode.
It is cleared by software reading I2C_SR2
register followed by a write in the I2C_OUT
register of the second address byte. It is also
cleared by hardware when the peripheral is
disabled (PE=0).
0: No ADD10 event occurred
1: The Master has sent the first address byte
When BTF is set, TRA=1 if a data byte has
been transmitted. It is cleared automatically
when BTF is cleared. It is also cleared by
hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1)
or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
This bit is set by hardware on detection of a
Start condition and cleared by hardware on
detection of a Stop condition. It indicates a
communication in progress on the bus. This
information is still updated when the interface
is disabled (PE=0).
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave
– SB=1 (Start condition generated in Mas-
– AF=1 (No acknowledge received after
– STOPF=1 (Stop condition detected in
– ARLO=1 (Arbitration lost in Master
– BERR=1 (Bus error, misplaced Start or
– Address byte successfully transmitted in
mode while ACK=1)
ter mode)
byte transmission)
Slave mode)
mode)
Stop condition detected)
Master mode.
Bit 3: BTF Byte transfer finished
Bit 2: ADSL Address matched (Slave Mode)
Bit 1: M/SL Master/Slave
Bit 0: SB Start bit (Master Mode)
0: No communication on the bus
1: Communication ongoing on the bus
This bit is set by hardware as soon as a byte
is correctly received or transmitted with
interrupt generation if ITE=1. It is cleared by
software reading I2C_SR1 register followed
by a read of I2C_IN or write of I2C_OUT
registers. It is also cleared by hardware when
the interface is disabled (PE=0).
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
This bit is set by hardware as soon as the
slave address received matched with the
OAR register content or a general call is
recognized. An interrupt is generated if
ITE=1. It is cleared by software reading
I2C_SR1 register or by hardware when the
interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
This bit is set by hardware as soon as the
interface
START=1). It is cleared by hardware after
detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled
(PE=0).
0: Slave mode
1: Master mode
This bit is set by hardware as soon as the
Start condition is generated (following a write
– Following a byte transmission, this bit is
– Following a byte reception, this bit is set
set after reception of the acknowledge
clock pulse. In case an address byte is
sent, this bit is set only after the EV6
event (see Figure 14.3). BTF is cleared
by reading I2C_SR1 register followed by
writing the next byte in I2C_OUT register.
after transmission of the acknowledge
clock pulse if ACK=1. BTF is cleared by
reading I2C_SR1 register followed by
reading the byte from I2C_IN register.
is
in
Master
mode
(writing