st52f510 STMicroelectronics, st52f510 Datasheet - Page 74

• Manufacturer Part Number: st52f510
• Description: 8-bit Intelligent Controller Unit Icu Two Timer/pwms, Adc, I2c, Spi, Sci
• Manufacturer: STMicroelectronics

ST52F510/F513/F514
When the Timers are in Reset status, or when the
device is reset, the TxOUT pins goes in threestate.
If these outputs are used to drive external devices,
it is recommended that the related pins be left in
the default configuration (Input threestate) or
change them in this configuration.
In PWM mode the PWM/Timers can only be Set or
Reset: Start/Stop signals do not affect the Timers.
TxRES resets the content of the 16-bit counter to
zero. It is generated by writing 0 in the
corresponding TxRES bit of the PWMx_CR1
Configuration Register and/or it can be driven by
the TRES pin if it is configured (only Timer0).
12.3.1 Simultaneous Start. The
can be started simultaneously when working in
PWM mode. The T0SYNC and T1SYNC bits in
PWM0_CR3 Configuration Registers mask the
reset of each timer; after enabling each single
PWM/Timer. They are started by putting off the
mask with a single writing in the PWM0_CR3
Register.
Simultaneous start is also possible in Timer mode.
The timers start counting simultaneously, but the
output pulses are generated according to the
modality configured (square or pulse mode).
12.4 Timer Interrupts
The PWM/Timer can be programmed to generate
an Interrupt Request, both on the falling and the
rising of the TxOUT signal and when there’s a
STOP signal (external or internal).
By using the TxIES, TxIER and TxIEF bits of the
Configuration Registers PWMx_CR1, the interrupt
sources can be switched on/off. All the interrupt
sources may be activated at the same time:
sources can be distinguished by reading the
PWMx_STATUS Input Register.
The interrupt on the falling edge corresponds to
half of a counting period in Timer mode when the
waveform is set to Square Wave and to the end of
the Ton phase in PWM mode.
Note: when the PWM Counter is set to 0 or 65535,
the interrupt occurs at the end of each control
period.
In order to be active, the PWM/Timers interrupts
must be enabled by writing the Interrupt Mask
Register
Register Space, bits MSKT0 And MSKT1.
74/106
(INT_MASK)
in
the
Configuration
PWM/Timers
12.5 PWM/Timer 0 Register Description
The following registers are related to the use of the
PWM/Timer 0.
12.5.1 PWM/Timer 0 Configuration Registers.
PWM/Timer 0 Control Register 1 (PWM0_CR1)
Configuration Register 9 (09h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: T0MOD PWM/Timer 0 Mode
Bit 6: T0IES Interrupt on Stop signal Enable
Bit 5: T0IEF Interrupt on T0OUT falling Enable
Bit 4: T0IER Interrupt on T0OUT rising Enable
Bit 3: STRMOD Start signal mode
Bit 2: T0STRT PWM/Timer 0 Start bit
Bit 1: RESMOD Reset signal mode
Bit 0: T0RES PWM/Timer 0 Reset bit
T0MOD
7
0: Timer Mode
1: PWM Mode
0: interrupt disabled
1: interrupt enabled
0: interrupt disabled
1: interrupt enabled
0: interrupt disabled
1: interrupt enabled
0: start on level
1: start on edge
0: Timer 0 stopped
1: Timer 0 started
0: reset on level
1: reset on edge
0: PWM/Timer 0 reset
1: PWM/Timer 0 set
T0IES
T0IEF
T0IER STRMOD T0STRT RESMOD T0RES
0