st52f510 STMicroelectronics, st52f510 Datasheet - Page 104

• Manufacturer Part Number: st52f510
• Description: 8-bit Intelligent Controller Unit Icu Two Timer/pwms, Adc, I2c, Spi, Sci
• Manufacturer: STMicroelectronics

ST52F510/F513/F514
Bit 7: SPIF Serial Peripheral data transfer flag.
Note: While the SPIF bit is set, all writes to the
SPI_OUT register are inhibited.
Bit 6: WCOL Write Collision status (read only).
Bit 5: OR SPI overrun error (read only).
Bit 4: MODF Mode Fault flag (read only).
Bit 3: Not used.
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This bit is set by hardware when a transfer
has
generated if SPIE=1 in the SPI_CR register.
It is cleared by a software sequence (an
access to the SPI_STATUS_CR register
followed by a read or write to the SPI_IN/
SPI_OUT registers).
0: Data transfer is in progress or has been
1: Data transfer between the device and an
This bit is set by hardware when a write to the
SPI_OUT register is done during a transmit
sequence. It is cleared by a software
sequence (see Figure 15.5).
0: No write collision occurred
1: A write collision has been detected
This bit is set by hardware when the byte
currently being received in the shift register is
ready to be transferred into the SPI_IN
register while SPIF = 1 (See Section 15.4.6
Overrun Condition). It is cleared by a
software
SPI_STATUS_CR register followed by a
read in SPI_IN or write of the SPI_OUT
register).
0: No overrun error.
1: Overrun error detected.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section
15.4.5 Master Mode Fault). An SPI interrupt
can be generated if SPIE=1 in the SPI_CR
register. This bit is cleared by a software
sequence
SPI_STATUS_CR register while MODF=1
followed by a write to the SPI_CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
(read only)
approved by a clearing sequence.
external device has been completed.
been
sequence
completed.
(An
access
(read
An
interrupt
to
of
the
the
is
Bit 2: SOD SPI output disable
Bit 1: SSM SS mode selection
Bit 0: SSI SS internal mode
Remark: It is recommended to write the SPI_CR
register after the SPI_STATUS_CR register when
working in master mode, vice versa when working
in slave mode.
15.5.2 SPI Input Register.
SPI Data Input Register (SPI_IN)
Input Register 5 (05h) Read only
Reset Value: 0000 0000 (00h)
bit 7-0: SPIDI7-SPIDI0 Received data.
The SPI_IN register is used to receive data on the
serial bus.
Note: During the last clock cycle the SPIF bit is set,
a copy of the data byte received in the shift register
is moved to a buffer. When the user reads the
serial peripheral data I/O register, the buffer is
actually being read.
SPIDI7
7
This bit is set and cleared by software. When
set, it disables the alternate function of the
SPI output (MOSI in master mode / MISO in
slave mode)
0: SPI output not disable
1: SPI output disable.
This bit is set and cleared by software. When
set, it disables the alternate function of the
SPI Slave Select pin and use the SSI bit
value instead of.
0: SS pin used by the SPI.
1: SS pin not used (I/O mode), SSI bit value
This bit is set and cleared by software. It
replaces pin SS of the SPI when bit SSM is
set to 1. SSI bit is active low slave select
signal when SSM is set to 1.
0 : Slave selected
1 : Slave not selected.
SPIDI6
is used.
SPIDI5
SPIDI4
SPIDI3
SPIDI2
SPIDI1
SPIDI0
0