ad5392bst-u2 Analog Devices, Inc., ad5392bst-u2 Datasheet - Page 35

• Manufacturer Part Number: ad5392bst-u2
• Description: 8-/16-channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-bit Voltage Output
• Manufacturer: Analog Devices, Inc.

AD539x to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done
by writing to the synchronous serial port control register
(SSPCON)—see the PIC16/17 Microcontroller User Manual.
In Figure 37, I/O port RA1 is used to pulse SYNC and enable
the serial port of the AD539x. This microcontroller transfers
only eight bits of data during each serial transfer operation;
therefore, three consecutive read/write operations are needed,
depending on the mode. Figure 37 shows the connection
diagram.
AD539x to 8051
The AD539x requires a clock synchronized to the serial data.
The 8051 serial interface must, therefore, be operated in Mode 0.
In this mode, serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 38 shows how the 8051 is
connected to the AD539x. Because the AD539x shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD539x
requires its data with the MSB first. Because the 8051 outputs
the LSB first, the transmit routine must take this into account.
PIC16C6x/7x
Figure 37. AD539x to PIC16C6x/7x Interface
SDO/RC5
SCK/RC3
SDI/RC4
RA1
DV
DD
RESET
SPI/I
SDO
DIN
SCLK
SYNC
AD539x
2
C
Rev. B | Page 35 of 44
AD539x to ADSP2101/ADSP2103
Figure 39 shows a serial interface between the AD539x and the
ADSP2101/ADSP2103. The
set up to operate in the SPORT transmit alternate framing
mode. The
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled.
Figure 39. AD539x to ADSP2101/ADSP2103 Interface
ADSP2101/ADSP2103
ADSP2101/
ADSP2103
8xC51
Figure 38. AD539x to 8051 Interface
RxD
P1.1
TxD
SCK
RFS
TFS
DR
DT
AD5390/AD5391/AD5392
DV
ADSP2101/ADSP2103
DD
DV
DV
DD
DD
SPORT is programmed
SPI/I
RESET
SDO
DIN
SCLK
SYNC
RESET
SPI/I
SDO
DIN
SCLK
SYNC
AD539x
AD539x
2
C
2
C
should be