ad5392bst-u2 Analog Devices, Inc., ad5392bst-u2 Datasheet - Page 16
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ad5392bst-u2
Manufacturer Part Number
ad5392bst-u2
Description
8-/16-channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-bit Voltage Output
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD5392BST-U2.pdf
(44 pages)
- Current page: 16 of 44
- Download datasheet (2Mb)
AD5390/AD5391/AD5392
Mnemonic
PD
SPI/I
SCLK/SCL
DIN/SDA
Exposed Pad
(LFCSP only)
2
C
Function
Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes
1 μA analog current and 20 μA digital current. In power-down mode, all internal analog circuitry is placed in low power
mode; the analog output is configured as high impedance outputs or provides a 100 kΩ load to ground, depending on
how the power-down mode is configured. The serial interface remains active during power-down.
Interface Select Input Pin. When this input is low, I
Interface Clock Input Pin. In SPI-compatible serial interface mode, this pin acts as a serial clock input. It operates at clock
speeds up to 50 MHz.
I
compatible with both 100 kHz and 400 kHz operating modes.
Interface Data Input Pin.
SPI/I
SPI/I
This pad should be connected to the ground plane.
2
C mode: In I
2
2
C = 1: This pin acts as the serial data input. Data must be valid on the falling edge of SCLK.
C = 0, I
2
C mode: In I
2
C mode, this pin performs the SCL function, clocking data into the device. Data transfer rate in I
2
C mode, this pin is the serial data pin (SDA) operating as an open drain input/output.
Rev. B | Page 16 of 44
2
C mode is selected. When this input is high, SPI mode is selected.
2
C mode is
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