isl3874 Intersil Corporation, isl3874 Datasheet - Page 6

• Manufacturer Part Number: isl3874
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor With Mini-pci
• Manufacturer: Intersil Corporation

MWE/ MWEL
PIN NAME
PIN NAME
RAMCS
MLBE
NVCS
MOE
PK0
PK1
PK2
PK3
PK4
PK7
PJ4
PJ5
PJ6
PJ7
PL3
PL7
PIN NUMBER
PIN NUMBER
K2
K1
L3
L1
L2
P4
R5
R4
N7
R6
P7
P8
T2
T4
T3
T5
T6
6
CMOS BiDir Output, 2mA, 50K Pull Up
CMOS TS Output, 2mA, 50K Pull Up
CMOS TS Output, 2mA, 50K Pull Up
CMOS TS Output, 2mA, 50K Pull Up
CMOS TS Output, 2mA, 50K Pull Up
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, ST, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Up
CMOS BiDir, 2mA, 50K Pull Down
TABLE 2. MEMORY INTERFACE PINS (Continued)
PIN I/O TYPE
TABLE 3. GENERAL PURPOSE PORT PINS
PIN I/O TYPE
ISL3874
MBUS Lower Byte Enable. Asserted when accessing the low-order
byte of x16 memory devices that use the JEDEC 5-wire control
interface.
Memory Output Enable; asserted on memory reads
Low (or only) Byte Memory Write Enable. Asserted on writes to x8
memory devices, x16 memory devices that use the JEDEC 5-wire
control inteface, or writes to the low-order byte of x16 memory
devices that use the JEDEC 4-wire control interface.
RAM Select; asserted on MBUS cycles when the address is in the
area configured as RAM
NV Memory Select; asserted on MBUS cycles when the address is in
the area configured as non-volitile memory.
PE1. PE1 and PE2 are bit-encoded functions that
control the RF and IF sections.
LE_IF. LE_IF and LE_RF are the corresponding serial
enables for the IF and RF chips. The trailing edge of the
latch enables (LE) are required to latch the data in the
input register. The last 20 bits of data before the trailing
edge of enables are latched in.
LED1.
RADIO_PE. This signal is the power enable to the RF
and IF components, but not the baseband.
LE_RF. LE_RF and LE_IF are the corresponding serial
enables for the RF and IF chips. The trailing edge of the
latch enables (LE) are required to latch the data in the
input register. The last 20 bits of data before the trailing
edge of enable are latched in.
SYNTHCLK. Separate signals, SYNTHCLK and
SYNTHDATA, are used to program the synthesizer
through bit manipulation in firmware.
SYNTHDATA. Separate signals, SYNTHDATA and
SYNTHCLK, are used to program the synthesizer
through bit manipulation in firmware.
PA_PE. This signal, when asserted high, enables the
Tx section of the Modulator/Demodulator and RF/IF
up/down converter circuits.
PE2. PE2 and PE1 are bit-encoded functions that
control the RF and IF sictions.
CAL_EN. Calibrates the Rx function to eliminate DC
offset in the Rx chain.
TR_SW_BAR. Antenna Diversity Control
TR_SW. Antenna Diversity Control
DESCRIPTION OF FUNCTION
DESCRIPTION
(IF OTHER THAN IO PORT)