isl3874 Intersil Corporation, isl3874 Datasheet - Page 28

• Manufacturer Part Number: isl3874
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor With Mini-pci
• Manufacturer: Intersil Corporation

to 2 bits. In the CCK mode, when a symbol decision error is
made, up to 6 bits may be in error although on average only 3
bits will be in error. Secondly, when the bits are processed by
the descrambler, these errors are further extended. The
descrambler is a 7-bit shift register with two taps exclusive or’ed
with the bit stream. Thus, each error is extended by a factor of
three. Multiple errors can be spaced the same as the tap
spacing, so they can be canceled in the descrambler. In this
case, two wrongs do make a right. Given all that, if a single
CORRELATOR OUTPUT IS THE RESULT OF CORRELATING
TX_AGC_IN
TX_IF_AGC
THE PN SEQUENCE WITH THE RECEIVED SIGNAL
ANTSEL
ANTSEL
V
I
REF
REF
T0
6-BIT
DAC
6-BIT
28
ADC
V
DD
FIGURE 16. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
(ANALOG)
AT 2X CHIP
TX_PE
SAMPLES
RATE
GENERATOR
TIMING
CORRELATION TIME
MCLK
REGISTER
CONTROL
TX AGC
BBP_CLK
FIGURE 17. CORRELATION PROCESS
GND (ANALOG)
T0 + 1 SYMBOL CORRELATOR
MODULATOR,
BARKER/CCK
ISL3874
TRANSMIT
OUTPUT REPEATS
FILTER
CONTROL
error is made the whole packet is discarded anyway, so the
error extension property has no effect on the packet error rate.
It should be taken into account if a forward error correction
scheme is contemplated.
Descrambling is self synchronizing and is done by a
polynomial division using a prescribed polynomial. A shift
register holds the last quotient and the output is the exclusive-
or of the data and the sum of taps in the shift register.
STATE
V
TX
DD
(DIGITAL)
PREAMBLE/HEADER
SCRAMBLER
GENERATOR
TX_DATA
CRC-16
CORRELATION
PEAK
EARLY
ON-TIME
LATE
GND (DIGITAL)
T0 + 2 SYMBOLS
DAC
DAC
TXI
TXQ
TX_RDY
TXCLK
TXD
MAC
CONTROL
SIGNALS