ad6472 Analog Devices, Inc., ad6472 Datasheet
ad6472
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ad6472 Summary of contents
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... Analog Devices. 2 Pair/1 Pair ETSI Compatible GENERAL DESCRIPTION The AD6472 is a single chip analog front end for two pair or single pair HDSL applications that use 1168 Kbps or 2.32 Mbps data rates. The AD6472 integrates all the transmit and receive functional blocks together with the timing recovery DAC ...
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... AD6472–SPECIFICATIONS P arameter TRANSMIT CHANNEL SNR THD TRANSMIT DAC Clock Frequency Resolution Update Rate Output Voltage TRANSMIT FILTER 1 Corner Frequency (3 dB) Accuracy Gain LINE DRIVER VCM Output Power Output Voltage TRANSMIT VOLTAGE LEVEL RECEIVE CHANNEL SNR THD HYBRID INTERFACE Input Voltage Range ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6472 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AD6472 Pin Mnemonic Description 1 +5 V_DVDD +5 V Digital Supply. 2 DGND Digital Ground. 3 MODE_SEL0 Bit Rate—Filter Corner Select. 4 MODE_SEL1 Bit Rate—Filter Corner Select. 5 AA_FLTR_BP Antialiasing Filter Bypass. PWRDN 6 Power-Down Active Low Connect. 8 TX_GAIN_SEL Transmit Attenuation (6 dB) Select. 9 TX_DRVR_BP Transmit Driver Bypass. ...
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... Circuit Description The AD6472 is an HDSL analog front end for either 2-pair or single pair applications. Transmit Channel The AD6472 receives, from a DSP transceiver core, a serial 2s complement data stream. The data are 16-bit words and the MSB is received first. The 12-bit DAC converts the digital data to an analog signal. ...
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... The ADC can be clocked at 2320 kHz, maxi- mum. Output data is provided in 2s complement form. Timing Recovery D/A The AD6472 has an integrated D/A converter to control an external VCXO used for timing recovery. The D bits and monotonic. The D/A accepts 7 bits inverted format input data TO PGA serially with the MSB first ...
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... D1 OUTPUT WORD FULL SCALE 011111111111 1/2 FULL SCALE 000000000000 1/2 FULL SCALE 111111111111 MINUS 1LSB ZERO 100000000000 Figure 5. Transmit Interface Timing Diagram –7– AD6472 DATA1 Parameter Min Typ Max Clock Period 862 Clock Pulsewidth High 342 514 Clock Pulsewidth Low 514 ...
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... AD6472 t 12ns SU t 10ns H SCLK 1 SFRAME D6 SDATA D5 D4 MSB 1. THE RISING EDGE OF SFRAME CAN OCCUR ANYWHERE. SFRAME MUST BE AT LEAST ONE CLOCK CYCLE WIDE. 2. SFRAME FALLING EDGE MUST OCCUR BEFORE THE SCLK RISING EDGE THAT CAPTURED THE SERIAL LSB. THIS ENSURES CORRECT LOADING INTO THE DAC. ...