sm5838a Nippon Precision Circuits Inc, (NPC), sm5838a Datasheet - Page 7

• Manufacturer Part Number: sm5838a
• Description: 5120 ? 8-bit Synchronous Fifo
• Manufacturer: Nippon Precision Circuits Inc, (NPC)

Write Cycle
The input data address is determined by the write address pointer position. The write address pointer is reset by
RW (write reset cycle), and is incremented on the rising edge of CLK whenever WE is LOW. Data input occurs
on the rising edge of CLK at the end of the write cycle.
When WE goes HIGH, write operation is disabled and the write address pointer stops.
Read Cycle
The output data address is determined by the read address pointer position. The read address pointer is reset by
RR (read reset cycle), and is incremented on the rising edge of CLK whenever RE is LOW. Data output starts
t
rising edge of CLK.
When RE goes HIGH, read operation is disabled and the read address pointer stops.
Note that data being read was written at least 20 write cycles previously (FIFO minimum delay). Therefore, if
(write address pointer) − (read address pointer) = 1 to 19, then a possibility exists that data from the preceding
line is output instead.
A
(max) after the rising edge of CLK at the start of the read cycle and continues until t
CLK
DIN
DOUT
WE
CLK
RE
(n-1)
(n-1)
t
CKW
t
CKW
t
A
n cycle
n cycle
t
t
CKW
DS
(n)
t
CKW
(n)
t
t
DH
WEH
t
t
OH
t
n+1 cycle
REH
A
n+1 cycle
t
t
WES
(n+1)
DS
t
SM5838AS
RES
(n+1)
t
t
WEH
DH
disable cycle
t
REH
disable cycle
t
WES
t
RES
RR="H" , OE="L"
RW="H"
t
t
SEIKO NPC CORPORATION —7
n+2 cycle
OH
A
n+2 cycle
OH
(min) after the next
(n+2)
(n+2)