st72f321r STMicroelectronics, st72f321r Datasheet - Page 23

• Manufacturer Part Number: st72f321r
• Description: 64/44-pin 8-bit Mcu With 32 To 60k Flash/rom, Adc, Five Timers, Spi, Sci, I2c Interface
• Manufacturer: STMicroelectronics

6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in
For more details, refer to dedicated parametric
section.
Main features
I
I
I
I
Figure 11. Clock, Reset and Supply Block Diagram
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
– Clock Security System (CSS) with Clock Filter
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
System Integrity Management (SI)
RESET
OSC2
OSC1
capability for monitoring the main supply or
the EVD pin
and Backup Safe Oscillator (enabled by op-
V
V
EVD
SS
DD
Figure
OSCILLATOR
RESET SEQUENCE
MULTI-
(MO)
MANAGER
(RSM)
11.
f
OSC
(option)
PLL
f
OSC2
SICSR
AVD AVD AVD LVD
SYSTEM INTEGRITY MANAGEMENT
S
0
1
CLOCK SECURITY SYSTEM
IE
CLOCK
FILTER
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 151.
Figure 10. PLL Block Diagram
f
OSC
AVD Interrupt Request
AUXILIARY VOLTAGE
F
tion byte)
LOW VOLTAGE
(CSS)
RF
DETECTOR
DETECTOR
(LVD)
(AVD)
0
SAFE
OSC
PLL x 2
CSS
IE
/ 2
CSS Interrupt Request
OSC2 =
CSS
D
WDG
f
RF
OSC2
f
PLL OPTION BIT
OSC
/2.
CLOCK (MCC/RTC)
WITH REALTIME
0
1
TIMER (WDG)
CONTROLLER
MAIN CLOCK
WATCHDOG
OSC2
f
ST72321
OSC2
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f
CPU