st72321j STMicroelectronics, st72321j Datasheet - Page 176

• Manufacturer Part Number: st72321j
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, 5 Timers, Spi, Sci, I2c Interface
• Manufacturer: STMicroelectronics

ST72321J
15 IMPORTANT NOTES
15.1 Unexpected Reset Fetch
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
15.2 Notes specific to ROM Devices only
15.2.1 I/O Port D Configuration
When using an external quartz crystal or ceramic
resonator, the f
cause the device goes into reserved mode control-
led by Port D.
This happens with either one of the following con-
figurations:
– PD[3:1]=010 while CSS and PLL options are
176/179
both disabled and PD4 is toggling
OSC2
clock may be disturbed be-
– PD[4:1]=1010 while CSS or PLL options are en-
This is detailed in the following table:
As a consequence, for cycle-accurate operations,
these configurations are prohibited in either input
or output mode.
Workaround:
To avoid this occurring, it is recommended to con-
nect one of these pins to GND (PD2 or PD4) or
V
CSS PLL PD[3:1]
DD
abled
ON
x
x
(PD1 or PD3).
ON
x
x
010
010
PD4
Tog-
gling
1
Max. 2 clock cy-
cles lost at each
rising or falling
edge of PD4
Max. 1 clock cy-
cle lost out of
every 16
Disturbance
Clock