st10f269z1 STMicroelectronics, st10f269z1 Datasheet - Page 169

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st10f269z1

Manufacturer Part Number
st10f269z1
Description
St10f269 16-bit Mcu With Mac Unit, 256k Byte Flash Memory And 12k Byte Ram
Manufacturer
STMicroelectronics
Datasheet

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ST10F269
V
Table 51 : CLKOUT and READY Characteristics (TQFP144 devices)
Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
Note
t
t
t
t
t
t
t
t
t
t
t
t
29
30
31
32
33
34
35
36
37
58
59
60
DD
Symbol
= 5V
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time
for deactivating READY.
The 2t
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
A
and t
10%, V
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Synchronous READY
setup time to CLKOUT
Synchronous READY
hold time after CLKOUT
Asynchronous READY
low time
Asynchronous READY
setup time
Asynchronous READY
hold time
Async. READY hold time after
RD, WR high (Demultiplexed
Bus)
C
refer to the next following bus cycle, t
SS
Parameter
= 0V, T
A
= -40 to + 125°C, C
1)
1)
2)
Minimum
-3 + t
31.25
9.625
5.625
45.25
Maximum CPU Clock
F
14
14
refers to the current bus cycle.
4
4
0
A
L
= 32MHz
= 50pF, TQFP144 devices
Maximum
+ t C + t
+7 + t
0 + 2t
31.25
4
4
A
A
F
2
2TCL + 14
Minimum
TCL – 10
TCL – 6
-3 + t
2TCL
1/2TCL = 1 to 32MHz
Variable CPU Clock
14
14
4
4
0
A
TCL - 15.625 +
2t
Maximum
A
+7 + t
+ t C + t
2TCL
4
4
A
F
2
169/184
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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