st10f269z1 STMicroelectronics, st10f269z1 Datasheet - Page 152

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st10f269z1

Manufacturer Part Number
st10f269z1
Description
St10f269 16-bit Mcu With Mac Unit, 256k Byte Flash Memory And 12k Byte Ram
Manufacturer
STMicroelectronics
Datasheet

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21.4.10 - Multiplexed Bus
V
ALE cycle time = 6 TCL + 2t
Table 46 : Multiplexed Bus Characteristics (PQFP144 devices)
152/184
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
22
23
25
27
38
39
40
DD
Symbol
= 5V
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
SR
CC
10%, V
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD, WR
(with RW-delay)
ALE falling edge to RD, WR (no
RW-delay)
Address float after RD, WR
(with RW-delay)
Address float after RD, WR
(no RW-delay)
RD, WR low time
(with RW-delay)
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address/Unlatched CS to valid
data in
Data hold after RD
rising edge
Data float after RD
Data valid to WR
Data hold after WR
ALE rising edge after RD, WR
Address/Unlatched CS hold
after RD, WR
ALE falling edge to Latched CS
Latched CS low to Valid Data In
Latched CS hold after RD, WR
(no RW-delay)
(with RW-delay)
(no RW-delay)
SS
Parameter
= 0V, T
A
+ t
A
= -40 to +125°C, C
C
+ t
F
(75ns at 40MHz CPU clock without wait states, PQFP144 devices).
1
1
1
1
15.5 + t
-8.5 + t
28 + t
10 + t
15 + t
10 + t
27 + t
4 + t
2 + t
4 + t
4 + t
-4 - t
4 + t
min.
Max. CPU Clock
0
A
A
A
A
F
A
C
C
F
F
F
= 40MHz
A
C
L
= 50pF,
18.5 + t
22 + 2t
18.5 + t
16.5 + t
+ t
10 - t
6 + t
max.
18.5
18.5
A
2t
t
6
C
+ t
A
C
A
A
C
C
C
F
+
+
3 TCL - 10.5 + t
2 TCL - 8.5 + t
TCL - 10.5 + t
2 TCL -9.5 + t
3 TCL -9.5 + t
2 TCL -15 + t
2 TCL -10 + t
2 TCL -15 + t
TCL - 8.5 + t
TCL - 8.5 + t
TCL - 8.5 + t
-8.5 + t
-4 - t
min.
1/2 TCL = 1 to 40MHz
Variable CPU Clock
0
A
A
A
A
A
C
F
F
C
C
A
F
F
2 TCL - 8.5 + t
2 TCL - 19 + t
3 TCL - 19 + t
3 TCL - 19
4 TCL - 28
3 TCL - 19
+ 2t
+ t
+ t
TCL + 6
10 - t
max.
C
A
A
6
+ 2t
+ t
+ t
A
ST10F269
C
C
A
C
C
F
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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