50s116t Ceramate Technical Co., Ltd., 50s116t Datasheet - Page 5

• Manufacturer Part Number: 50s116t
• Description: Sdram 512k X 2 Banks X 16 Bits Sdram
• Manufacturer: Ceramate Technical Co., Ltd.

* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:[phone]
Fax:[phone]
5. PIN DESCRIPTION
PIN NUMBER
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
7, 13, 38, 44,
4, 10, 41, 47
20
27
48, 49
36, 14
26, 50
33, 37
1, 25
19
18
17
16
15
35
34
24,
32
DQ0
PIN NAME
A0
UDQM/
LDQM
V
V
CKE
RAS
CAS
CLK
V
V
NC
BA
WE
CS
CC
SS
CC
SS
A10
DQ15
Q
Q
Row Address
Clock Enable CKE controls the clock activation and deactivation.
Write Enable Referred to
Input/Output
Clock Inputs System clock used to sample inputs on the rising edge
Bank Select Select bank to activate during row address latch time,
FUNCTION
Chip Select Disable or enable the command decoder. When
Connection
Data Input/
Ground for
(+3.3V) for
I/O buffer
I/O buffer
Address
Address
Column
(+3.3V)
Ground
Output
Strobe
Strobe
Power
Power
Mask
No
Multiplexed pins for row and column address.
Row address: A0 A10. Column address: A0
or bank to read/write during column address latch time.
Multiplexed pins for data input and output.
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock,
operation to be executed.
Referred to
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
of clock.
When CKE is low, Power-down mode, Suspend mode,
or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V
improve noise immunity.
Separated ground from V
improve noise immunity.
No connection
Page 5 of 42
RAS
RAS
RAS
,
CAS
DESCRIPTION
CC
SS
Email: [e-mail]
Http: www.ceramate.com.tw
and
, used for output buffers to
, used for output buffers to
WE
50S116T
define the
Rev 1.0 Aug.20,2002
A7.
SDRAM