50s116t Ceramate Technical Co., Ltd., 50s116t Datasheet - Page 11

• Manufacturer Part Number: 50s116t
• Description: Sdram 512k X 2 Banks X 16 Bits Sdram
• Manufacturer: Ceramate Technical Co., Ltd.

* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
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The Power-down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t
enabled with CKE held high for a period equal to t
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when
edge of the clock. A No Operation Command will not terminate a previous operation that is still
executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when
cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one-clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
CS
is brought high, the RAS ,
CS
is low with RAS ,
Page 11 of 42
CKS
(min) + t
CK
CAS , and
(min).
CAS , and
CK
. The input buffers need to be
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held high at the rising
signals become don't
50S116T
Rev 1.0 Aug.20,2002
SDRAM