50s116t Ceramate Technical Co., Ltd., 50s116t Datasheet - Page 35

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50s116t

Manufacturer Part Number
50s116t
Description
Sdram 512k X 2 Banks X 16 Bits Sdram
Manufacturer
Ceramate Technical Co., Ltd.
Datasheet
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Fax:886-3-3521052
Operating Timing Example, continued
Auto Precharge Timing (Read Cycle)
(1) CAS Latency=2
(2) CAS Latency=3
( a ) burst length = 1
( b ) burst length = 2
( c ) burst length = 4
( d ) burst length = 8
( a ) burst length = 1
( b ) burst length = 2
( c ) burst length = 4
( d ) burst length = 8
Command
Command
Command
Command
Command
Command
Command
Command
DQ
Note:
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Read
Read
Read
Read
Read
Read
Read
Read
0
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t
Read
Act
AP
AP
AP
1
Q0
AP
Q0
AP
Q0
Q0
t
represents the Bank Activate command.
represents the Read with Auto precharge command.
2
RP
represents the start of internal precharging.
t
RP
Q1
Q0
Q0
Q0
Q0
Act
Q1
Q1
t
3
RP
t
RP
Page 35 of 42
Q2
Act
Q1
AP
Q1
Q1
Act
AP
Q2
4
Act
Q2
Q2
Q3
Q3
t
5
RP
RAS
t
RP
(min).
Q3
Q3
Act
Q4
6
Act
Q4
Q5
7
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
AP
Q5
AP
Q6
8
Q6
Q7
t
50S116T
9
RP
Rev 1.0 Aug.20,2002
t
RP
Q7
Act
10
SDRAM
Act
11

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