si3200-x-gs Silicon Laboratories, si3200-x-gs Datasheet - Page 71
si3200-x-gs
Manufacturer Part Number
si3200-x-gs
Description
Dual Programmable Cmos Slic With Line Monitoring
Manufacturer
Silicon Laboratories
Datasheet
1.SI3200-X-GS.pdf
(128 pages)
- Current page: 71 of 128
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IRQ3: Interrupt Status 3 (Register Address 17)
(Register type: Operational/bits writable in GCI mode only)
Reset settings = 0x00
Name CMBALS
Type
Bit
Bit
7
6
5
4
3
2
1
0
Reserved
CMBALS
R/W
Name
PQ6S
PQ5S
PQ4S
PQ3S
PQ2S
PQ1S
D7
D6
Common Mode Balance Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending.
Read returns zero.
Power Alarm Q6 Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending.
Power Alarm Q5 Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending.
Power Alarm Q4 Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending.
Power Alarm Q3 Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending.
Power Alarm Q2 Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending.
Power Alarm Q1 Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending.
PQ6S
R/W
D5
PQ5S
Preliminary Rev. 0.96
R/W
D4
PQ4S
R/W
D3
Function
PQ3S
R/W
D2
PQ2S
R/W
D1
PQ1S
R/W
D0
Si3232
71
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