si514 Silicon Laboratories, si514 Datasheet - Page 15

• Manufacturer Part Number: si514
• Description: Any-frequency I 2c Programmable Xo 100 Khz To 250 Mhz
• Manufacturer: Silicon Laboratories

3. All-Digital PLL Applications
The Si514 uses a high resolution divider M that enables fine frequency adjustments with resolution better than
0.026 parts per billion. Fine frequency adjustments are useful when making frequency corrections that compensate
for changing ambient conditions, long term aging or when locking the Si514 to an input clock reference. Figure 3
shows a typical implementation using a system IC such as an FPGA to control the output of the Si514 in a phase-
locked application. Refer to “AN575: An Introduction to FPGA-Based ADPLLs” for more information.
Since small frequency changes must be within ±1000 ppm of the center frequency, HS_DIV and LS_DIV remain
constant. The below expression can be used to calculate a new M
frequency shift, where ∆F
Some systems, particularly those that use feedback control, can simplify the computation by implementing an
approximate frequency change based on toggling a bit position or adding/subtracting a bit to the existing M_Frac
value. Since M ranges approximately ±10% between 65.04065041 and 78.17385866, the effect of changing
M_Frac by a single bit depends only slightly on the absolute value of M.
For M=71 near the midpoint of the range, toggling M_Frac[0] changes the output frequency by 0.026 ppb. Each
higher order bit doubles the influence such that toggling M_Frac[1] is 0.052 ppb, M_Frac[2] is 0.1 ppb, etc. Figure 4
shows this trend across multiple registers generalized to M_Frac[N]. Coarse changes greater than ±1.7 ppm are
possible but most applications require finer transitions. Toggling each bit involves incrementing or decrementing
the bit position. Writing M_Int[8:3] in register 9 completes the operation.
Fin
FPGA
M_Int[8:0] = 000100111
÷
Figure 3. All-Digital PLL Application Using Si514 with Dual CMOS Output
Figure 4. Output Frequency Change When Toggling M_Frac[N], M=71
PD
M = 71.000000000000
Loop
Filter
OUT
is in ppm.
Conversion
Command
M_Frac[28:0] = 00000000000000000000000000000
÷
M
Master
2
I
2
C
Preliminary Rev. 0.9
=
M
1

1 F
SCL
SDA
–
OUT
M_Frac[23:16] = 00000000

10
M_Frac[15:8] = 00000000
–
6

2
M_Frac[7:0] = 00000000
divider value based on a desired output
Any Frequency
I
2
C Control
DSPLL
1.7ppm
6.7ppb
Si514
0.026ppb
Si514
CLK_OUT
FB
15