74LVC16374ADGG,118 NXP Semiconductors, 74LVC16374ADGG,118 Datasheet - Page 14

• Manufacturer Part Number: 74LVC16374ADGG,118
• Description: IC 16BIT EDGE TRIG D FF 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Type Busr

Specifications of 74LVC16374ADGG,118

• Package / Case: 48-TSSOP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Output Type: Tri-State Non Inverted
• Function: Standard
• Current - Output High, Low: 24mA, 24mA
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Delay Time - Propagation: 7ns
• Frequency - Clock: 100MHz
• Trigger Type: Positive Edge
• Number Of Circuits: 2
• Logic Family: LVC
• Logic Type: CMOS
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 14 ns
• High Level Output Current: - 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.2 V
• Technology: CMOS
• Number Of Bits: 16
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Low Level Output Current: 24mA
• Operating Supply Voltage (min): 1.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935235190118

NXP Semiconductors
Fig 12. Package outline SOT362-1 (TSSOP48)
74LVC_LVCH16374A_7
Product data sheet
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT362-1
48
1
Z
max.
y
1.2
A
pin 1 index
0.15
0.05
A
1
1.05
0.85
A
2
IEC
0.25
A
3
e
D
0.28
0.17
b
p
All information provided in this document is subject to legal disclaimers.
MO-153
JEDEC
0.2
0.2
0.1
0.1
c
REFERENCES
12.6
12.4
D
(1)
Rev. 07 — 23 March 2010
0
b
74LVC16374A; 74LVCH16374A
p
E
6.2
6.0
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
(2)
w
JEITA
scale
M
2.5
0.5
25
24
e
H
8.3
7.9
c
E
5 mm
L
A
1
2
A
1
0.8
0.4
L
p
0.50
0.35
Q
H
E
E
PROJECTION
detail X
EUROPEAN
0.25
v
L
L
0.08
p
w
Q
(A )
0.1
© NXP B.V. 2010. All rights reserved.
y
3
ISSUE DATE
A
99-12-27
03-02-19
θ
0.8
0.4
Z
A
X
SOT362-1
v
M
8
0
θ
o
o
14 of 19
A