74LVC16374ADGG,118 NXP Semiconductors, 74LVC16374ADGG,118 Datasheet - Page 10

• Manufacturer Part Number: 74LVC16374ADGG,118
• Description: IC 16BIT EDGE TRIG D FF 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Type Busr

Specifications of 74LVC16374ADGG,118

• Package / Case: 48-TSSOP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Output Type: Tri-State Non Inverted
• Function: Standard
• Current - Output High, Low: 24mA, 24mA
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Delay Time - Propagation: 7ns
• Frequency - Clock: 100MHz
• Trigger Type: Positive Edge
• Number Of Circuits: 2
• Logic Family: LVC
• Logic Type: CMOS
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 14 ns
• High Level Output Current: - 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.2 V
• Technology: CMOS
• Number Of Bits: 16
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Low Level Output Current: 24mA
• Operating Supply Voltage (min): 1.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935235190118

NXP Semiconductors
11. Waveforms
74LVC_LVCH16374A_7
Product data sheet
Fig 7.
Fig 8.
Measurement points are given in
V
Measurement points are given in
The shaded areas indicate when the input is permitted to change for predictable performance.
V
Data set-up and hold times for the nDn input to the nCP input
Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency
OL
OL
and V
and V
OH
OH
are the typical output voltage levels that occur with the output load.
are the typical output voltage levels that occur with the output load.
nQn output
nCP input
nDn input
nQn output
nCP input
GND
GND
V
Table
Table
V
OH
OL
GND
V
V
V
All information provided in this document is subject to legal disclaimers.
V
I
I
OH
OL
V
I
8.
8.
Rev. 07 — 23 March 2010
74LVC16374A; 74LVCH16374A
V
V
t
PHL
M
M
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
t
W
V
V
t
M
su
M
1/f
max
t
h
V
M
t
V
PLH
M
t
su
001aaa256
t
h
001aaa257
© NXP B.V. 2010. All rights reserved.
10 of 19