sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 65

• Manufacturer Part Number: sc3200
• Description: Geode-tm Sc3200 Processor
• Manufacturer: Advanced Micro Devices

Signal Definitions
3.4.2
AMD Geode™ SC3200 Processor Data Book
Signal Name
MD[63:0]
MA[12:0]
BA1
BA0
CS1#
CS0#
RASA#
CASA#
WEA#
DQM7
DQM6
DQM5
DQM4
DQM3
DQM2
DQM1
DQM0
CKEA
Memory Interface Signals
Table 3-3
Table 3-3
on page
on page
EBGA
AK29
AC30
AC28
AL26
AF31
AJ20
AJ26
AJ21
M31
See
See
P31
P30
P29
N31
N30
N29
T28
38.
38.
Ball No.
TEPBGA
Table 3-5
Table 3-5
on page
on page
AK14
AH27
AK12
AH12
AB31
AG29
AK21
AC31
AG30
AH23
AL12
AL15
AL11
AL22
AJ13
AJ12
See
See
54.
54.
Type
I/O
O
O
O
O
O
O
O
O
Description
Memory Data Bus. The data bus lines
driven to/from system memory.
Memory Address Bus. The multiplexed row/
column address lines driven to the system
memory. Supports 256-Mbit SDRAM.
Bank Address Bits. These bits are used to
select the component bank within the
SDRAM.
Chip Selects. These bits are used to select
the module bank within system memory.
Each chip select corresponds to a specific
module bank. If CS# is high, the bank(s) do
not respond to RAS#, CAS#, and WE# until
the bank is selected again.
Row Address Strobe. RAS#, CAS#, WE#
and CKE are encoded to support the different
SDRAM commands. RASA# is used with
CS[1:0]#.
Column Address Strobe. RAS#, CAS#,
WE# and CKE are encoded to support the
different SDRAM commands. CASA# is used
with CS[1:0]#.
Write Enable. RAS#, CAS#, WE# and CKE
are encoded to support the different SDRAM
commands. WEA# is used with CS[1:0]#.
Data Mask Control Bits. During memory
read cycles, these outputs control whether
SDRAM output buffers are driven on the MD
bus or not. All DQM signals are asserted dur-
ing read cycles.
During memory write cycles, these outputs
control whether or not MD data is written into
SDRAM.
DQM[7:0] connect directly to the [DQM7:0]
pins of each DIMM connector.
Clock Enable. These signals are used to
enter Suspend/power-down mode. CKEA is
used with CS[1:0]#.
If CKE goes low when no read or write cycle
is in progress, the SDRAM enters power-
down mode. To ensure that SDRAM data
remains valid, the self-refresh command is
executed. To exit this mode, and return to
normal operation, drive CKE high.
These signals should have an external pull-
down resistor of 33 KΩ.
Revision 5.1
Mux
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