ds26503 Maxim Integrated Products, Inc., ds26503 Datasheet - Page 26

• Manufacturer Part Number: ds26503
• Description: T1/e1/j1 Bits Element
• Manufacturer: Maxim Integrated Products, Inc.

6. HARDWARE CONTROLLER INTERFACE
In Hardware Controller mode, the parallel and serial port pins are reconfigured to provide direct access to
certain functions in the port. Only a subset of the device’s functionality is available in hardware mode.
Each register description throughout the data sheet indicates the functions that may be controlled in
hardware mode and several alarm indicators that are available in both hardware and processor mode.
Also indicated are the fixed states of the functions not controllable in hardware mode.
6.1 Transmit Clock Source
Refer to
CLOCK is selected by the TCSS0 and TCSS1 pins, as shown in
the same signal as select for TX CLOCK. If the user wants to slave the transmitter to the recovered
clock, then the RCLK pin must be tied to the TCLK pin externally.
Table 6-1. Transmit Clock Source
6.2 Internal Termination
In Hardware Controller mode, the internal termination is automatically set according to the receive or
transmit mode selected. It can be disabled via the TITD and RITD pins. If internal termination is enabled
in E1 mode, the E1TS pin is use to select 75Ω or 120Ω termination. The E1TS pin applies to both
transmit and receive.
Table 6-2. Internal Termination
TCSS1
PIN 31
0
0
1
1
PIN NAME
TITD
PIN 5
RITD
PIN 6
PIN 9
E1TS
Figure
TCSS0
PIN 63
0
1
0
1
3-3. In Hardware Controller mode, the input to the TX PLL is always TCLK PIN. TX
Transmit Internal Termination Disable. Disables the internal transmit
termination. The internal transmit termination value is dependent on the state of
the TMODEx pins.
Receive Internal Termination Disable. Disables the internal receive
termination. The internal receive termination value is dependent on the state of
the RMODEx pins.
E1 Termination Select. Selects 120Ω or 75Ω internal termination when one of
the E1 modes is selected and internal termination is enabled. IF E1 is selected for
both transmit and receive, then both terminations will be the same.
The TCLK pin is the source of transmit clock.
The PLL_CLK is the source of transmit clock.
The scaled signal present at MCLK as the transmit
clock.
The signal present at RCLK is the transmit clock.
0 = 75Ω
1 = 120Ω
TRANSMIT CLOCK SOURCE
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FUNCTION
Table
6-1. The PLL_OUT pin is always