ds26503 Maxim Integrated Products, Inc., ds26503 Datasheet
ds26503
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ds26503 Summary of contents
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... Synchronization Status Message (SSM) can also be recovered. The transmit portion can directly interface interfaces as well as source the SSM in T1 and E1 modes. The DS26503 can translate between any of the supported inbound synchronization clock rates to any supported outbound rate. A separate output is provided to source a 6312kHz clock ...
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FEATURES ....................................................................................................................................7 1.1 G .....................................................................................................................................7 ENERAL 1 ...........................................................................................................................7 INE NTERFACE 1 ITTER TTENUATOR 1 RAMER ORMATTER 1 EST AND IAGNOSTICS 1 ............................................................................................................................8 ONTROL ORT 2. SPECIFICATIONS COMPLIANCE.................................................................................................9 3. BLOCK ...
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E1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................46 9 ONTROL EGISTERS 9 NFORMATION EGISTERS 10. I/O PIN CONFIGURATION OPTIONS..........................................................................................52 11. T1 SYNCHRONIZATION STATUS MESSAGE ...........................................................................55 11 RIENTED 11.2 T BOC .........................................................................................................................55 ...
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N B ONMULTIPLEXED 19 .............................................................................................................................116 ERIAL US 19 ECEIVE IDE 19 RANSMIT IDE 20. REVISION HISTORY..................................................................................................................121 21. PACKAGE INFORMATION........................................................................................................122 .............................................................................................................113 US .......................................................................................118 HARACTERISTICS .....................................................................................119 HARACTERISTICS 4 of 122 ...
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Figure 3-1. Block Diagram ........................................................................................................................11 Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ........................................................................12 Figure 3-3. Transmit PLL Clock Mux Diagram..........................................................................................12 Figure 3-4. Master Clock PLL Diagram ....................................................................................................13 Figure 13-1. Basic Network Connection ...................................................................................................77 Figure 13-2. Typical Monitor Application ..................................................................................................79 ...
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Table 2-1. T1-Related Telecommunications Specifications........................................................................9 Table 2-2. E1-Related Telecommunications Specifications .....................................................................10 Table 5-1. LQFP Pinout ............................................................................................................................23 Table 6-1. Transmit Clock Source ............................................................................................................26 Table 6-2. Internal Termination ................................................................................................................26 Table 6-3. E1 Line Build-Out ....................................................................................................................27 Table 6-4. T1 Line Build-Out ....................................................................................................................27 Table ...
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FEATURES 1.1 General 64-pin, 10mm x 10mm LQFP package 3.3V supply with 5V-tolerant inputs and outputs Evaluation kits IEEE 1149.1 JTAG Boundary Scan Driver source code available from the factory 1.2 Line Interface Requires a single master clock (MCLK) ...
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Framer/Formatter Full receive and transmit path transparency T1 framing formats include D4 and ESF E1 framing formats include FAS and CRC4 Detailed alarm and status reporting with optional interrupt support RLOF, RLOS, and RAIS alarms interrupt on change of ...
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... SPECIFICATIONS COMPLIANCE The DS26503 meets all applicable sections of the latest telecommunications specifications including those in the following tables. Table 2-1. T1-Related Telecommunications Specifications ANSI T1.102 - Digital Hierarchy Electrical Interface ANSI T1.231 - Digital Hierarchy–Layer 1 in Service Performance Monitoring ANSI T1.403 - Network and Customer Installation Interface–DS1 Electrical Interface TR62411 (ANSI) “ ...
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Table 2-2. E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048kbps ITUT G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps ITUT G.772 ITUT G.775 ITUT G.823 ...
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... MASTER CLOCK CLOCK RTIP DATA LIU LIU RRING - DATA RLOS RAIS TTIP TX LIU JTAG PORT JTAG PORT JTAG PORT JTAG PORT JTMS JTRST JTCLK DS26503 JA CLOCK ENABLED ENABLED AND IN RX AND PATH PATH ...
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Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) CLOCK FROM RX + DATA LIU - DATA CLOCK DATA LIU - DATA Figure 3-3. Transmit PLL Clock Mux Diagram RECOVERED CLOCK TCLK PIN JA CLOCK JITTER ATTENUATOR ENABLED ...
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Figure 3-4. Master Clock PLL Diagram 13 of 122 ...
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PIN FUNCTION DESCRIPTION 4.1 Transmit PLL NAME TYPE Transmit PLL Output. This pin can be selected to output the 1544kHz, PLL_OUT O 2048kHz, 64kHz, or 6312kHz output from the internal TX PLL or the internal signal, TX CLOCK. See ...
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Receive Side NAME TYPE Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), or 6312kHz RCLK O (G.703 Synchronization Interface). Receive Sync T1/E1 Mode: An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (IOCR1.5 = ...
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... TMODE2 I to configure the transmit operating mode. Three-State Control and Device Reset. A dual-function pin. A zero-to-one transition issues a hardware reset to the DS26503 register set. Configuration TSTRST I register contents are set to the default state. Leaving TSTRST high three-states all output and I/O pins (including the parallel control port). Set low for normal operation ...
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NAME TYPE Data Bus D[5] or Address/Data Bus AD[5]/Receive Framing Mode Select Bit 1 A[5]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data bus D[5]. AD[5]/ I/O RMODE1 AD[5]: In multiplexed bus operation (BIS[1:0] = 00), ...
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NAME TYPE Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select 3/Master Out-Slave In A[1]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data bus D[1]. AD[1]/ AD[1]: In multiplexed bus operation (BIS[1:0] = 00), it serves ...
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... A0: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[0]. In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and A0/E1TS I should be tied low. E1TS: In Hardware Mode (BIS[1:0] = 11), selects the E1 internal termination value (0 = 75Ω 120Ω). DS26503 T1/E1/J1 BITS Element FUNCTION 19 of 122 ...
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NAME TYPE Bus Type Select/Transmit and Receive B8ZS/HDB3 Enable BTS: Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD (DS), ALE (AS), and WR BTS/HBE I (R/W) ...
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... T1 and E1 modes. MCLK I The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS26503 in T1-only operation, a 1.544MHz (50ppm) clock source can be used. Receive Tip. Analog input for clock recovery circuitry. This pin connects via a RTIP I 1:1 transformer to the network ...
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Power NAME TYPE Digital Positive Supply. 3.3V ±5%. Should be tied to the RVDD and TVDD DVDD — pins. Receive Analog Positive Supply. 3.3V ±5%. Should be tied to the DVDD and RVDD — TVDD pins. Transmit Analog Positive ...
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... Hardware Mode: MCLK Pre-Scaler Select 0 Parallel Port Mode: Address Latch Enable/Address Bus Bit 7 — MPS1 Serial Port Mode: Unused, should be connected to V Hardware Mode: MCLK Pre-Scaler Select 1 TCLK TCLK Transmit Clock Input 23 of 122 DS26503 T1/E1/J1 BITS Element FUNCTION ...
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... Parallel Port Mode: Bus Type Select (Motorola/Intel) Serial Port Mode: Unused, should be connected to V — HBE Hardware Mode: Receive and Transmit DB3/B8ZS Enable BIS0 BIS0 Bus Interface Select Mode 0 BIS1 BIS1 Bus Interface Select Mode 122 DS26503 T1/E1/J1 BITS Element FUNCTION . . . . ...
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... Serial Port Mode: Serial Data Out (Master In-Slave MIS0 TCSS0 Out) Hardware Mode: Transmit Clock Source Select 0 Parallel Port Mode: Address/Data Bus Bit 1 MOSI RMODE3 Serial Port Mode: Serial Data In (Master Out-Slave In) Hardware Mode: Receive Mode Select 122 DS26503 T1/E1/J1 BITS Element FUNCTION ...
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HARDWARE CONTROLLER INTERFACE In Hardware Controller mode, the parallel and serial port pins are reconfigured to provide direct access to certain functions in the port. Only a subset of the device’s functionality is available in hardware mode. Each register ...
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Line Build-Out Table 6-3. E1 Line Build-Out PIN 13 PIN 12 PIN 75Ω with high return loss (Note 120Ω with high return ...
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... Note 1: The DS26503 does not have an internal source for CAS signaling and multiframe alignment generation. CAS signaling, and the multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame aligned to sync signal on the TS pin. ...
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... Remote Loopback Enable: In this loopback, data input to the framer portion of the DS26503 will be transmitted back to the transmit portion of the LIU. Data will continue to RLB pass through the receive side framer of the DS26503 as it would normally and the data PIN 60 from the transmit side formatter will be ignored. ...
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... A serial SPI bus interface is selected when bus select is 10 (BIS[1:0] = 10). In this mode, a master/slave relationship is enabled on the serial port with three signal lines (SCK, MOSI, and MISO) and a chip select (CS), with the DS26503 acting as the slave. Port read/write timing is not related to the system read/write timing, thus allowing asynchronous, half-duplex operation. See the AC Electrical Characteristics section for the AC timing characteristics of the serial port ...
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... R/W bit, the target register address, and the Burst bit. After these two control bytes, the DS26503 responds with the requested data byte. After the first data byte, if the Burst bit is set, the DS26503 auto-increments its address counter and transmits the byte stored in the next higher address location ...
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Register Map Table 7-2. Register Map Sorted By Address ADDRESS TYPE 00 R/W Test Reset Register 01 R/W I/O Configuration Register 1 02 R/W I/O Configuration Register 2 03 R/W T1 Receive Control Register 1 04 R/W T1 Receive ...
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ADDRESS TYPE 44 R/W Transmit Remote Alarm Bits 45 R/W Transmit Sa4 Bits 46 R/W Transmit Sa5 Bits 47 R/W Transmit Sa6 Bits 48 R/W Transmit Sa7 Bits 49 R/W Transmit Sa8 Bits 4A R/W Transmit Sa Bit Control Register ...
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... Bits Unused, must be set = 0 for proper operation. Bits 4 and 5: Test Mode Bits (TEST0, TEST1). Test modes are used to force the output pins of the DS26503 into known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses ...
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... Register Address: 08h Bit # 7 6 Name TMODE3 TMODE2 Default TMODE3 TMODE2 Mode PIN 62 PIN 48 Bit Receive Mode Configuration (RMODE[3:0]). Used to select the operating mode of the receive path for the DS26503. RMODE3 RMODE2 RMODE1 ...
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... Note 1: The DS26503 does not have an internal source for CAS signaling and multiframe alignment generation. CAS signaling, and the multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame aligned to sync signal on the TS pin. ...
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Register Name: TPCR Register Description: Transmit PLL Control Register Register Address: 09h Bit # 7 6 Name TPLLOFS1 TPLLOFS0 Default Mode For more information on all the bits in the Transmit PLL control register, refer ...
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... The user will always precede a read of any of the status registers with a write. The byte written to the register will inform the DS26503 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on ...
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Information Registers Information registers operate the same as status registers except they cannot cause interrupts. INFO3 register is a read-only register and it reports the status of the E1 synchronizer in real time. INFO3 information bits are not latched, ...
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... T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS26503 is configured via a set of five control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26503 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration ...
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Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 Name — — Default Mode Bit 0: Receive Side D4 Yellow Alarm Select (RD4YM zeros in ...
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Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 Name TJC TFPT Default RMODEx 0 Mode PINS Bit 0: Transmit Yellow Alarm (TYEL not transmit yellow ...
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Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 Name TB8ZS TFSE Default HBE 1 Mode PIN 55 Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS ...
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... ANSI T1.403: No more than 15 consecutive zeros and at least N ones in each and every time window bits, where through 23. When this bit is set to one, the DS26503 forces the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to zero, as B8ZS encoded data streams cannot violate the pulse-density requirements ...
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... Note: The definition of Blue Alarm (or Alarm Indication Signal unframed, all-ones signal. Blue Alarm detectors should be able to operate properly in the presence of a 10E-3 error rate, and they should not falsely trigger on a framed, all-ones signal. The Blue Alarm criteria in the DS26503 has been set to achieve this performance. SET CRITERIA ...
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... E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS26503 is configured via a set of two control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26503 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration ...
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... CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error — TSiS — 122 DS26503 T1/E1/J1 BITS Element ITU SPEC. G.706 G.706 4.2 and 4.3.2 G.732 5 — THDB3 — HBE 0 0 PIN 55 4 ...
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... CSC0 is the LSB of the 6-bit counter. (Note: The second LSB, CSC1, is not accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits — — — CRCRC CSC3 CSC2 CSC0 FASSA 122 DS26503 T1/E1/J1 BITS Element FASRC CASRC CASSA CRC4SA ...
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... Bits 0 to 3:Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip. ID0 is the LSB of a decimal code that represents the chip revision. Bits Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS26503 ID. The DS26503 ID is 0001. ...
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... X Mode Bit 0: Receive Loss of Frame Condition (RLOF). Set when the DS26503 is not synchronized to the received data stream. Bit 1: Receive Loss Of Signal Condition (RLOS). Set when 255 (or 2048 if E1RCR mode or 192 T1 mode consecutive zeros have been detected. In 6312kHz Synchronization Interface Mode, this bit will be set when the signal received is out of range as defined by the G ...
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Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 17h Bit # 7 6 Name RYELC RAISC Default Mode Bit 0: Receive Loss of Frame Condition (RLOF interrupt masked 1 = ...
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I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 Name — RSMS2 Default Mode Bit 0: Output Data Format (ODF bipolar ...
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Table 10-1. TS Pin Functions TRANSMIT IOCR.3 IOCR.2 MODE T1/E1 0 T1/E1 0 T1/E1 0 T1/E1 0 Table 10-2. RLOF Pin Functions RECEIVE IOCR.4 MODE T1/E1 0 T1/E1 1 IOCR Frame sync input 0 1 Frame sync output ...
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Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 Name RCLKINV TCLKINV Default Mode Bits Unused, must be set = 0 for proper operation. Bit ...
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... Reserved For Network Synchronization Use 11.1 T1 Bit-Oriented Code (BOC) Controller The DS26503 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. In typical BITS applications, the BOC controller would be used to transmit and receive Synchronization Status Messages in T1 mode over the data link. ...
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Receive BOC The receive BOC function is enabled by setting BOCC The RFDL register will now operate as the receive BOC message and information register. The lower six bits of the RFDL register (BOC message bits) are ...
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Register Name: BOCC Register Description: BOC Control Register Register Address: 1Fh Bit # 7 6 Name — — Default Mode Bit 0: Send BOC (SBOC). Set = 1 to transmit the BOC code placed in ...
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Register Name: RFDL (RFDL register bit usage when BOCC Register Description: Receive FDL Register Register Address: 50h Bit # 7 6 Name — — Default Mode Bit 0: BOC Bit 0 (RBOC0) Bit ...
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Register Name: SR3 Register Description: Status Register 3 Register Address: 18h Bit # 7 6 Name RAIS-CI LOTC Default Mode Bit 0: Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a ...
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Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 19h Bit # 7 6 Name RAIS-CI LOTC Default Mode Bit 0: Receive BOC Detector Change-of-State Event (RBOC interrupt masked 1 = ...
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Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ah Bit # 7 6 Name — RSA1 Default Mode Bit 0: Receive Align Frame Event (RAF). (E1 only) Set every 250µs at the beginning ...
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Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Bh Bit # 7 6 Name — RSA1 Default Mode Bit 0: Receive Align Frame Event (RAF interrupt masked 1 = interrupt ...
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Register Name: TFDL Register Description: Transmit FDL Register Register Address: 51h Bit # 7 6 Name TFDL7 TFDL6 Default Mode Note: Also used to insert Fs framing pattern in D4 framing mode. The transmit FDL ...
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... E1 SYNCHRONIZATION STATUS MESSAGE The DS26503 provides access to both the transmit and receive Sa/Si bits. In E1, the Sa bits are used to transmit and receive the SSM. The primary method to access the Sa (and Si) bits is based on CRC4 multiframe access. An alternate method is based on double-frame access. Table 12-1. E1 SSM Messages ...
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Register Name: RSiAF Register Description: Receive Si Bits of the Align Frame Register Address: 58h Bit # 7 6 Name SiF0 SiF2 Default Mode Bit 0: Si Bit of Frame 14(SiF14) Bit 1: Si Bit ...
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Register Name: RRA Register Description: Receive Remote Alarm Register Address: 5Ah Bit # 7 6 Name RRAF1 RRAF3 Default Mode Bit 0: Remote Alarm Bit of Frame 15(RRAF15) Bit 1: Remote Alarm Bit of Frame ...
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Register Name: RSa5 Register Description: Receive Sa5 Bits Register Address: 5Ch Bit # 7 6 Name RSa5F1 RSa5F3 Default Mode Bit 0: Sa5 Bit of Frame 15(RSa5F15) Bit 1: Sa5 Bit of Frame 13(RSa5F13) Bit ...
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Register Name: RSa7 Register Description: Receive Sa7 Bits Register Address: 5Eh Bit # 7 6 Name RSa7F1 RSa7F3 Default Mode Bit 0: Sa7 Bit of Frame 15(RSa7F15) Bit 1: Sa7 Bit of Frame 13(RSa7F13) Bit ...
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Register Name: TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: 42h Bit # 7 6 Name TsiF0 TsiF2 Default Mode Bit 0: Si Bit of Frame 14(TsiF14) Bit 1: Si Bit ...
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Register Name: TRA Register Description: Transmit Remote Alarm Register Address: 44h Bit # 7 6 Name TRAF1 TRAF3 Default Mode Bit 0: Remote Alarm Bit of Frame 15(TRAF15) Bit 1: Remote Alarm Bit of Frame ...
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Register Name: TSa5 Register Description: Transmit Sa5 Bits Register Address: 46h Bit # 7 6 Name TSa5F1 TSa5F3 Default Mode Bit 0: Sa5 Bit of Frame 15(TSa5F15) Bit 1: Sa5 Bit of Frame 13(TSa5F13) Bit ...
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Register Name: TSa7 Register Description: Transmit Sa7 Bits Register Address: 48h Bit # 7 6 Name TSa7F1 TSa7F3 Default Mode Bit 0: Sa7 Bit of Frame 15(TSa7F15) Bit 1: Sa7 Bit of Frame 13(TSa7F13) Bit ...
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Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: 4Ah Bit # 7 6 Name SiAF SiNAF Default Mode Bit 0: Additional Bit 8 Insertion Control Bit (Sa8 not ...
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Alternate Sa/Si Bit Access Based on Double-Frame On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and Si bit locations. The RAF and RNAF registers are updated on ...
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Register Name: RNAF Register Description: Receive Non-Align Frame Register Register Address: 57h Bit # 7 6 Name Si 1 Default Mode Bit 0: Additional Bit 8 (Sa8) Bit 1: Additional Bit 7 (Sa7) Bit 2: ...
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Register Name: TNAF Register Description: Transmit Non-Align Frame Register Register Address: 41h Bit # 7 6 Name Si 1 Default 0 1 Bit 0: Additional Bit 8 (Sa8) Bit 1: Additional Bit 7 (Sa7) Bit 2: Additional Bit 6 (Sa6) ...
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... The DS26503 can switch between networks without changing any external components on either the transmit or receive side. In this configuration the DS26503, using a fixed 120Ω external termination, can connect to T1, J1, E1, or 6312kHz without any component change. The receiver can adjust the 120Ω termination to 100Ω, 110Ω or 75Ω ...
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... E1 and 0dB to –36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6000ft (T1) in length. The DS26503’s LIU is designed to be fully software selectable for E1 and T1 without the need to change any external resistors for the receive-side. The receiver will allow the user to configure the DS26503 for 75Ω ...
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... MCLK, the TCLK pin or the TX PLL. See the TX PLL clock mux diagram in Figure 3-3 . Due to the nature of the design of the transmitter in the DS26503, very little jitter (less than 0.005 UI broadband from 10Hz to 100kHz) is added to the jitter present on the selected transmit clock P-P source ...
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... Setting JACKS0 (LIC2.3) to logic 0 bypasses this PLL. 13.5 Jitter Attenuator The DS26503’s jitter attenuator can be set to a depth of either 32 bits or 128 bits via the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the attenuation are shown in ...
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... Jitter Attenuator Limit Trip (JALT) bit in Status Register 1 (SR1.4). 13.6 CMI (Code Mark Inversion) Option The DS26503 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B type of signal. Ones are encoded as either a logical one or zero level for the full duration of the clock period ...
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... Note 2: TT0, TT1, and TT2 of LIC4 register must be set to zero in this configuration. N.M. = not meaningful EGL JAS JABDS PIN 11 N (NOTE 1) 1:2 1:2 1:2 1 122 DS26503 T1/E1/J1 BITS Element DJA TPD RETURN LOSS (NOTE 1) N.M. N.M. 21dB 21dB 11.6Ω 6.2Ω ...
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T1 Mode APPLICATION DSX 133 feet)/0dB CSU DSX-1 (133 to 266 feet DSX-1 (266 to 399 feet DSX-1 (399 to 533 feet) 1 ...
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Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 31h Bit # 7 6 Name JACKS1 LIRST Default Mode Bit 0: Custom Line Driver Select (CLDS). Setting this bit to a one will ...
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Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 32h Bit # 7 6 Name CMIE CMII Default Mode Bit 0: Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern at TTIP ...
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Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 33h Bit # 7 6 Name MPS1 MPS0 Default MPS1 MPS0 Mode PIN 16 PIN 15 Bits Receive Termination Select (RT0 to RT2) ...
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Register Name: INFO1 Register Description: Information Register 1 Register Address: 11h Bit # 7 6 Name — — Default Mode Bits Receive Level Bits (RL0 to RL3). Real-time bits. RL3 RL2 RL1 ...
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Register Name: SR1 Register Description: Status Register 1 Register Address: 14h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 for proper operation. ...
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Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 15h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 for proper ...
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... The area under this portion of the circuit should not contain power planes. Note 3: Some T1 (never in E1) applications source or sink power from the network-side center taps of the Rx/Tx transformers. A list of transformer part numbers and manufacturers is available by contacting Note 4: www.maxim-ic.com/support. DESCRIPTION 90 of 122 DS26503 T1/E1/J1 BITS Element ...
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... Some T1 (never in E1) applications source or sink power from the network-side center taps of the Rx/Tx transformers. Note 5: The ground trace connected to the S2/S3 pair and the S4/S5 pair should be at least 50 mils wide to conduct the extra current from a longitudinal power-cross event. DS26503 T1/E1/J1 BITS Element DESCRIPTION 91 of 122 ...
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Figure 13-6. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 Figure 13-7. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ...
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... Figure 13-8. Jitter Tolerance (T1 Mode) 1K 100 10 1 0.1 1 Figure 13-9. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DS26503 Tolerance TR 62411 (Dec. 90) ITU-T G.823 10 100 1K FREQUENCY (Hz) DS26503 Tolerance 1.5 Minimum Tolerance Level as per ITU G.823 20 10 100 1k FREQUENCY (Hz 122 10K 100K 0.2 2.4k 18k 10k 100k ...
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... Figure 13-10. Jitter Attenuation (T1 Mode) 0 -20 -40 -60 1 Figure 13-11. Jitter Attenuation (E1 Mode) 0 -20 -40 -60 1 Curve A Curve B DS26503 T1 MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area Prohibited Area DS26503 E1 MODE 10 100 1K FREQUENCY (Hz 122 TR 62411 (Dec. 90) Prohibited Area 10K 100K ITU G.7XX 10K 100K ...
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... Bit 2: Remote Loopback (RLB). In this loopback, data received at RTIP and RRING will be looped back to the transmit LIU. Received data will continue to pass through the receive side framer of the DS26503 as it would normally and the data from the transmit side formatter will be ignored. ...
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... SYNCHRONIZATION INTERFACE The DS26503 has a 6312kHz Synchronization Interface mode of operation that conforms with Appendix II.2 of G.703, with the exception that the DS26503 transmits a square wave as opposed to the sine wave that is defined in the G.703 specification. 15.1 Receive 6312kHz Synchronization Interface Operation On the receive interface, a 6312kHz sine wave is accepted conforming to the input port requirements of G ...
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... JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26503 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26503 contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan ...
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 16-2 . Test-Logic-Reset Upon power-up, the TAP controller will be in the ...
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Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and will initiate a scan sequence for the ...
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Figure 16-2. TAP Controller State Diagram Test Logic 1 Reset 0 Run Test/ 0 Idle 1 1 Select DR-Scan Capture DR 0 Shift Exit DR 0 Pause Exit2 ...
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Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the shift-IR state, the instruction shift register will be connected between JTDI ...
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... IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional test register has been included with the DS26503 design. This test register is the identification register and is used with the IDCODE instruction and the test-logic-reset state of the TAP controller ...
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Table 16-4. Boundary Scan Control Bits CELL # NAME 0 AD1 1 AD1_7_CTRL 2 AD0 3 AD0_CTRL 4 WR_RW 5 RD_DS BIS1 8 BIS0 9 BTS 10 THZE 11 TMODE1 12 TMODE2 13 PLL_CLK 14 INT 15 ...
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... AD7 41 AD6 42 AD5 43 AD4 44 AD3 45 AD2 * This pin is not bonded out on the DS26503 package, however, it must be accounted for in the chain. CONTROL TYPE CELL observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only Output3 1 Output3 1 Output3 ...
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FUNCTIONAL TIMING DIAGRAMS 17.1 Processor Interface 17.1.1 Parallel Port Mode See the AC Timing section. 17.1.2 SPI Serial Port Mode Figure 17-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 SCK CS MOSI 1 0 ...
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Figure 17-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 SCK CS MOSI MSB MISO Figure 17-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 SCK CS ...
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Figure 17-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 SCK CS MOSI MSB MISO Figure 17-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 SCK CS ...
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... Operating Temperature Range for DS26503L…………………………………………………………0°C to +70°C Operating Temperature Range for DS26503LN……………………………………………-40°C to +85°C (Note 1) Storage Temperature Range… ...
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... Table 18-5. DC Characteristics = 3.3V ±5 0°C to +70°C for DS26503L DS26503LN.) PARAMETER SYMBOL Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) Note 6: 0.0V < V < Applied to INT when three-stated. Note 7: = 3.3V ±5 MIN TYP -1 -1 +4.0 ...
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... AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals and 20pF for all others. 19.1 Multiplexed Bus Table 19-1. AC Characteristics, Multiplexed Parallel Port = 3.3V ±5 0°C to +70°C for DS26503L DS26503LN.) (Note 1, Figure 19-1 PARAMETER Cycle Time Pulse Width, DS Low or RD High ...
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Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) ALE t ASD AD0-AD7 Figure 19-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00) ALE t ASD RD t ASD WR ...
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Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1: ASD AD0-AD7 (read) CS AD0-AD7 (write) A8 & ASH t ASED t RWS t t DDR ASL t AHL ...
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... Nonmultiplexed Bus Table 19-2. AC Characteristics, Non-Mux Parallel Port = 3.3V ±5 0°C to +70°C for DS26503L (Note 1, DS26503LN.) Figure PARAMETER Setup Time for A0 to A7, Valid to CS Active Setup Time for CS Active to Either RD, WR Active Delay Time from Either Active to Data Valid ...
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Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1: 0ns min RD Figure 19-5. Intel Bus Write Timing (BTS = 0 / BIS[1: ...
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Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1: R/W CS 0ns min. DS Figure 19-7. Motorola Bus Write Timing (BTS = 1 / BIS[1: ...
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... Serial Bus Table 19-3. AC Characteristics, Serial Bus = 3.3V ±5 0°C to +70°C for DS26503L DS26503LN.) (Note 1, Figure 19-8 DIAGRAM CHARACTERISTIC (NOTE 3) NUMBER Operating Frequency (NOTE 2) Slave 1 Cycle Time: Slave 2 Enable Lead Time 3 Enable Lag Time Clock (CLK) High Time 4 Slave Clock (CLK) Low Time ...
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Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1: INPUT CLK INPUT CPOL = 0 2 CLK INPUT CPOL = 1 8 MISO INPUT 6 MOSI OUTPUT NOTE: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST ...
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... Receive Side AC Characteristics Table 19-4. Receive Side AC Characteristics = 3.3V ±5 0°C to +70°C for DS26503L DS26503LN.) (Note 1, Figure 19-10 PARAMETER RCLK Period RCLK Pulse Width RCLK Pulse Width RCLK to RSER Delay RCLK to RS Delay Note 1: The timing parameters listed in this table are guaranteed by design (GBD). ...
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Transmit Side AC Characteristics Table 19-5. Transmit Side AC Characteristics = 3.3V ±5 -40°C to +85°C.) (Note 1 and DD A PARAMETER TCLK Period TCLK Pulse Width TCLK Rise and Fall Times TX CLOCK Setup ...
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Figure 19-11. Transmit Timing, T1/ TCLK RCLK, JA CLOCK 4 PLL_OUT TX CLOCK 3 TSER 1 TS_8K_4 TS_8K_4 2 (REFER TO THE TRANSMIT PLL BLOCK DIAGRAM, NOTE OUTPUT MODE. NOTE 2: ...
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... C are guaranteed by design GBD and not production tested. to Operating Temp Range for DS26503LN. Renumbered notes for Table 18-1 to Table 18-5. (Page 16) Clarified RITD and TITD descriptions. (Page 19) For E1TS description, changed 0 = 120Ω and 1 = 75Ω 75Ω and 1 = 120Ω. ...
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... The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. 122 of 122 © 2007 Maxim Integrated Products DS26503 T1/E1/J1 BITS Element ...