ds22-l100-041 Conexant Systems, Inc., ds22-l100-041 Datasheet - Page 30

• Manufacturer Part Number: ds22-l100-041
• Description: Cx84100-41/-23 Scxv.22bis Modem V.22bis Modem With Cx20493 Smartdaa? Line Side Device
• Manufacturer: Conexant Systems, Inc.

Table 3-2. CX84100 V.22bis Modem Pin Signal Definitions (Continued)
3-6
RTS#
TDCLK#
RDCLK#
Notes:
I/O Types: See Table 3-3.
Label
10
8
6
Pin
CX84100-41/-23 SCXV.22bis Modem Data Sheet
V.24 (EIA/TIA-232-E) DTE Serial Interface (Continued)
I
O
O
I/O
Itpu/Ot2
It/Ot2
It/Ot2
I/O Type
Conexant
Request To Send (EIA CA/ITU-T CT105). The DTE uses this
signal when it wants to transmit to the DCE. This signal, in
combination with the Clear To Send (CTS) signal, coordinates
data transmission between the DTE and the DCE.
A logic 0 on this line keeps the DCE in transmit mode. The DCE
will receive data from the DTE to be forwarded to the
communication link.
The RTS and CTS signals relate to a half-duplex telephone line.
A half duplex line is capable of carrying signals on both directions
but only one at a time. When the DTE has data to send, it raises
RTS, and then waits until the DCE changes from receive to
transmit mode. The logic 1 to 0 transition of the RTS instructs the
DCE to switch to "transmit" mode, and when a transmission is
possible, the DCE sets CTS and transmission can begin.
On a full duplex line, like a hard-wired connection, where
transmission and reception can occur simultaneously, the CTS
and RTS signals are held to a constant logic 0 level. A logic 0 to
1 transition of the RTS instructs the DCE to complete data
transmission and to switch to a “receive” (or “no transmission”)
mode.
Transmit Serial Clock. The DCE sends the DTE a clock signal
on this line. This enables the DTE to transmit serial data on the
Transmitted Data line (TXD). The clock frequency is the same as
the bit rate (±0.01%) of TXD with a duty cycle of 50±1%.
TDCLK# signal transition from logic 0 to 1 marks the center of
each bit on TXD. Leave open if not used.
Receive Serial Clock. The DCE sends the DTE a clock signal on
this line. RDCLK clocks the reception circuitry of the DTE, which
receives serial data on the Received Data line (RXD). The clock
frequency is the same as the bit rate (±0.01%) of RXD with a duty
cycle of 50±1%. RDCLK# signal transition from logic 0 to 1
indicates the center of each signal bit on RXD. Leave open if not
used.
Signal Name/Description
102339C