cy22701 Cypress Semiconductor Corporation., cy22701 Datasheet - Page 5

• Manufacturer Part Number: cy22701
• Description: 1 Pll In-system Programmable Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07698 Rev. *B
DCXO
The default clock configuration of the CY22701 has 256 stored
values that are used to adjust the frequency of the crystal oscil-
lator, by changing the load capacitance. In order to use these
stored values, the clock configuration must be reprogrammed
to enable the DCXO feature.
To Configure for DCXO Operation
Once the clock configuration block is programmed for DCXO
operation, the SPI may be used to dynamically change the
capacitor load value on the crystal. A change in crystal load
capacitance corresponds with a change in the reference
frequency. Thus, the crystal oscillator frequency can be
adjusted from –150 ppm of the nominal frequency value to
+150 ppm of the nominal frequency value. “Nominal frequency
– 150 ppm” is achieved by writing 00000000 into the CapLoad
register, and “nominal frequency + 150 ppm” is achieved by
writing 11111111 into the CapLoad register
Write Protect (WP) Registers
To reconfigure pin 7 as WP, to control enable/disable of write
protection, use the SPI to write the following:
WPSrc, Register 11H[3] = 0
CLK2, Register 09H[4] = 0
CLKSRC 2,1,0, Register 45H[3:1] = 111
When active (WP = 1), WP prevents the control logic for the
EE from initiating a erase/program cycle for the EEPROM
blocks. All serial shifting works as normal.
To reconfigure pin 7 as CLK2, use the SPI to write the
following:
WPSrc, Register 11H[3] = 1
CLK2, Register 09H[4] = 1
CLKSRC 2,1,0, Registers 45H[3:1] = see Table 11
Table 6. Q Counter Register Definition
Table 7. P Counter Register Definition
• XCapSrc, Register 12H[5] = 0
• XDRV[1:0], Register 12H[4:3] = (see Table 2)
Register
Address
42H
40H
41H
42H
PB(7)
PO
PO
D7
D7
1
PB(6)
Q(6)
Q(6)
D6
D6
1
PB(5)
Q(5)
Q(5)
D5
D5
0
PRELIMINARY
Pump(2)
PB(4)
Q(4)
Q(4)
D4
D4
PLL Frequency, Q Counter
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7-bit variable with
a maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2
is added to this register value to achieve the total Q, or Q
Q
Q
The minimum value of Q
is 129. Register 42H is defined in Table 6.
Stable operation of the CY22701 cannot be guaranteed if
REF/Q
are defined in Table 6.
PLL Frequency, P Counter
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Q
VCO frequency. The product counter, defined as P
made up of two internal variables, PB and PO. The formula for
calculating P
P
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings (see section, Charge Pump Settings
[40H(2..0)] on page 6”). The 3 MSBs of register 40H are preset
and reserved and cannot be changed.
PO is a single bit variable, defined in register 42H(7). This
allows for odd numbers in P
The remaining 7 bits of 42H are used to define the Q counter,
as shown in Table 6.
The minimum value of P
is 2055. To achieve the minimum value of P
should both be programmed to 0. To achieve the maximum
value of P
should be programmed to 1.
Stable operation of the CY22701 cannot be guaranteed if the
value of (P
100 MHz. Registers 40H, 41H and 42H are defined in Table 7.
total
total
total
is defined by the formula:
= (2(PB + 4) + PO)
= Q + 2.
total
Pump(1)
PB(3)
Q(3)
Q(3)
D3
D3
total
falls below 250 kHz. Q
total
total
, PB should be programmed to 1023, and PO
*(REF/Q
is:
Pump(0)
PB(2)
Q(2)
Q(2)
total
total
total
D2
D2
)) is above 400 MHz or below
total
is 2. The maximum value of Q
is 8. The maximum value of P
.
total
total
PB(9)
PB(1)
bit locations and values
Q(1)
Q(1)
D1
D1
) value to achieve the
total
CY22701
Page 5 of 15
, PB and PO
PB(8)
PB(0)
Q(0)
Q(0)
D0
D0
total
total
, is
total
total
.