cy22701 Cypress Semiconductor Corporation., cy22701 Datasheet
cy22701
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cy22701 Summary of contents
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... Industry standard packaging saves on board space Input Frequency Range OUTPUT ) DIVIDERS VCO P PLL EEPROM Memory Array • 3901 North First Street CY22701 Output Frequency Range 80 kHz – 200 MHz (3.3V) {Commercial} 80 kHz –167 MHz (3.3V) {Industrial} Output Crosspoint Switch CLK1 Array CLK2 Pin Configuration 8 ...
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... The CY22701 is a group of two slave devices with addresses as shown in Figure 1. The serial programming interface address of the CY22701 clock configuration 2-kbit EEPROM block is 68H ...
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... CLK = REF/Post Divider CLK = REF The basic PLL block diagram is shown in Figure 2. Each of the two clock outputs on the CY22701 has a total of seven output options available to it. There are six post divider options available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N and DIV2N are independently calculated and are applied to individual output groups ...
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... For an external clock source, CapLoad defaults to 1. See Table 5 for CapLoad bit locations and values. The input load capacitors are placed on the CY22701 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply and temperature changes ...
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... DCXO The default clock configuration of the CY22701 has 256 stored values that are used to adjust the frequency of the crystal oscil- lator, by changing the load capacitance. In order to use these stored values, the clock configuration must be reprogrammed to enable the DCXO feature. To Configure for DCXO Operation • ...
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... Table 9. Charge Pump Settings Charge Pump Setting – Pump(2..0) 000 001 010 011 100 101, 110, 111 Pump(2) Pump(1) CY22701 DIV1N(2) DIV1N(1) DIV1N(0) DIV2N(2) DIV2N(1) DIV2N(0) total values below 16 total values above 1023 are needed, use total Calculated P total 16– ...
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... DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8. Reserved – Do not use CLKSRC1 CLKSRC0 CLKSRC2 for CLK1 for CLK1 for CLK2 CLKOE for CLKOE for CLK2 CLK1 CY22701 CLKSRC1 CLKSRC0 1 for CLK2 for CLK2 Page ...
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... Through random read operations, the master may access any memory location. To perform this type of read operation, first the word address must be set. This is accomplished by sending the address to the CY22701 as part of a write operation. After the word address is sent, the master generates a START condition following the acknowledge. This terminates the write operation before any data is stored in the address, but not before the internal address pointer is set ...
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... ACK ACK ACK ACK 8-bit 8-bit Register Register Data Data (XXH) (X0H) Stop Signal 16 byte wrap 1 Bit 1 Bit 1 Bit 1 Bit Master Master Master Master ACK ACK ACK ACK 8-bit 8-bit Register Register Data Data (8FFH) (000H) Stop Signal CY22701 Page ...
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... Figure 6. Start and Stop Frame + ACK RA7 RA6 RA1 RA0 + Comments Fundamental mode Ratio used because typical R are much less than the maximum spec No external series resistor assumed High side NOM Low side NOM CY22701 SDAT SCLK STOP + ACK ACK + Min. Typ. – 14 – ...
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... CMOS levels Except XTAL pins [3] Current drawn while part is in standby. Description – may be powered at any value between 3.465 and 2.375. DDL CY22701 Max. 7.0 125 100 V + 0 0.5 DD 2000 1,000,000 (100k/page) Min. Typ. Max. 3.135 3.3 3.465 – ...
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... Ramp time from 1.5V to 2.5V Wait time after a write to EEPROM is initiated by the stop bit until V fails below 2.5V DD CLK , 20–80 LOW DD CLK , 80–20 HIGH DD Square noise spike on input OUTPUTS GND reaches 1.5V, it must ramp to 2.5V within 15 ms. DD CY22701 Min. Typ. Max. Unit 0.8 1.4 – V/ns 0.8 1.4 – ...
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... Field Programmable CY22701FSXIT Field Programmable Document #: 38-07698 Rev. *B PRELIMINARY Figure 8. Duty Cycle Definition Package Name Lead Free SOIC Lead Free SOIC - Tape and Reel Lead Free SOIC Lead Free SOIC - Tape and Reel CY22701 / 0 Operating ...
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... SZ08.15 LEAD FREE PKG. SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0°~8° 0.0098[0.249 system, provided that the system conforms to the I CY22701 MAX. PART # 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.016[0.406] 0.0098[0.249] 0.035[0.889] ...
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... Document History Page Document Title: CY22701 1 PLL In-System Programmable Clock Generator Document Number: 38-07698 Orig. of REV. ECN NO. Issue Date Change ** 226712 See ECN *A 318313 See ECN *B 320154 See ECN Document #: 38-07698 Rev. *B PRELIMINARY Description of Change RGL New data sheet RGL swapped CLK2 to CLK1 in Summary and CLKOE Bit Setting Tables. ...