cy28446 Cypress Semiconductor Corporation., cy28446 Datasheet - Page 9

• Manufacturer Part Number: cy28446
• Description: Clock Generator For Intel Calistoga Chipset
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-00168 Rev *D
Byte 9: Control Register 8
.
Crystal Recommendations
The CY28446 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28446 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
14.31818 MHz
Frequency
Bit
7
6
5
4
3
2
1
0
(Fund)
Figure 1. Crystal Capacitive Clarification
@Pup
0
0
0
0
0
1
1
1
Cut
AT
Loading Load Cap
Parallel
Reserved
Reserved
Reserved
PCIF0
Name
PCI3
PCI2
PCI1
PCI0
20 pF
0.1 mW
33-MHz Output drive strength
0 = Low, 1 = High
33-MHz Output drive strength
0 = Low, 1 = High
33-MHz Output drive strength
0 = Low, 1 = High
33-MHz Output drive strength
0 = Low, 1 = High
33-MHz Output drive strength
0 = Low, 1 = High
Reserved set to 1
Reserved set to 1
Reserved set to 1
(max.)
Drive
Shunt Cap
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
(max.)
5 pF
Cs1
Motional
0.016 pF
Figure 2. Crystal Loading Example
(max.)
Ce1
X1
Ci1
Description
Clock Chip
XTAL
Tolerance
35 ppm
(max.)
Ci2
X2
Ce2
Stability
30 ppm
(max.)
Cs2
CY28446
3 to 6p
33 pF
Pin
Trim
Page 9 of 21
2.8 pF
Trace
Aging
(max.)
5 ppm
[+] Feedback