cy28446 Cypress Semiconductor Corporation., cy28446 Datasheet - Page 8

• Manufacturer Part Number: cy28446
• Description: Clock Generator For Intel Calistoga Chipset
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-00168 Rev *D
Byte 6: Control Register 6
Byte 7: Vendor ID
Byte 8: Control Register 7
Bit
Bit
Bit
1
7
6
5
4
3
2
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
HW
HW
HW
0
0
1
0
1
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
REF/N or Tri-state Select REF/N or Tri-state Select
outputs except those set
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
PCI and PCIF clock
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
to free running
SRC[T/C]10
SRC[T/C]9
SRC[T/C]8
Test Mode
Reserved
Reserved
Reserved
SRC10
Name
Name
SRC9
SRC8
FS_C
Name
FS_B
FS_A
REF
1 = REF/N, 0 = Tri-state
Test Mode Control
1 = Ref/N or Tristate, 0 = Normal Operation
Reserved set to 1
REF Output Drive Strength
0 = Low, 1 = High
SW PCI_STP Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI and PCIF outputs will be
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI and PCIF outputs will resume
in a synchronous manner with no short pulses.
FSC Reflects the value of the FS_C pin sampled on power-up
0 = FSC was low during VTT_PWRGD# assertion
FSB Reflects the value of the FS_B pin sampled on power-up
0 = FSB was low during VTT_PWRGD# assertion
FSA Reflects the value of the FS_A pin sampled on power-up
0 = FSA was low during VTT_PWRGD# assertion
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Reserved set to 0
SRC[T/C]10 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]9 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]8 Output Enable
0 = Disable (Tri-state), 1 = Enable
Reserved set to 0
Allow control of SRC[T/C]10 with assertion of OEA#
0 = Free running, 1 = Stopped with OEA#
Allow control of SRC[T/C]9 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
Allow control of SRC[T/C]8 with assertion of OEA#
0 = Free running, 1 = Stopped with OEA#
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Description
Description
Description
CY28446
Page 8 of 21
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