cy28rs680-2 SpectraLinear Inc, cy28rs680-2 Datasheet - Page 7

• Manufacturer Part Number: cy28rs680-2
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
Byte 9: Clock Request Mapping Register (continued)
Byte 10: Dynamic Frequency Register4
Byte 11: WDT System Register
Bit
Bit
Bit
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
0
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
0
0
0
0
0
SMSW_SEL_Bypass
Recovery_Frequency
WD_TIMER2
WD_TIMER1
WD_TIMER0
SMSW_SEL
CLKREQC#
CLKREQC#
CLKREQC#
Time_Scale
Timer_SEL
WD_Alarm
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WD_EN
Name
Name
Name
INFORMATION
ADVANCE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CLKREQC# Controls ATIG2
0 = Not controlled, 1 = Controlled
CLKREQC# Controls ATIG1
0 = Not controlled, 1 = Controlled
CLKREQC# Controls ATIG0
0 = Not controlled, 1 = Controlled
Reserved
Reserved
Reserved
Reserved
Smooth switch on/off
0: on 1: off
Smooth Switch Select
0: Select CPU_PLL (PLL1) 1: Select ATIG_PLL (PLL2)
This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0: Use HW settings, 1: Recovery N[8:0]
Timer_SEL selects the WD reset function at SRESET pin when WD time
out.
0 = Reset and Reload Recovery_Frequency
1 = Only Reset
Time_Scale allows selection of WD time scale
0 = 294 ms, 1 = 2.34 s
WD_Alarm is set to “1” when the watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp.
Watchdog timer time stamp selection
000: Reserved (test mode)
001: 1 * Time_Scale
010: 2 * Time_Scale
011: 3 * Time_Scale
100: 4 * Time_Scale
101: 5 * Time_Scale
110: 6 * Time_Scale
111: 7 * Time_Scale
Watchdog timer enable, when the bit is asserted, Watchdog timer is
triggered and time stamp of WD_Timer is loaded
0 = Disable, 1 = Enable
Description
Description
Description
CY28RS680-2
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