cy28rs680-2 SpectraLinear Inc, cy28rs680-2 Datasheet - Page 10

• Manufacturer Part Number: cy28rs680-2
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ[A:C]# Description
The CLKREQ#[A:C] signals are active LOW inputs used for
clean stopping and starting selected SRC outputs. The
CLKREQ# signal is a de-bounced signal in that its state must
remain unchanged during two consecutive rising edges of
DIFC to be recognized as a valid assertion or deassertion.
(The assertion and deassertion of this signal is absolutely
asynchronous.)
CLe
Total Capacitance (as seen by the crystal)
=
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
Ce = 2 * CL – (Cs + Ci)
1
Figure 3. RESET_IN# Assertion/Deassertion Waveform
+
1
Ce2 + Cs2 + Ci2
INFORMATION
1
ADVANCE
)
CLK_REQ[A:C]# Assertion
The impact of asserting the CLKREQ#[A:C] pins is that all DIF
outputs that are set in the control registers to stoppable via
assertion of CLKREQ#[A:C] are to be stopped after their next
transition. The final state of all stopped DIF signals is tristate,
both SRCT clock and SRCC clock outputs will be driven
Tristate.
CLK_REQ[A:C]# Deassertion
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the deassertion to active outputs is between 2 and 6 SRC
clock periods (2 clocks are shown) with all SRC outputs
resuming simultaneously.
RESET_IN# Assertion
The RESET_IN# is a negative edge triggered signal. When
asserted, all PLLs will revert back to a safe default frequency.
The clock output will be allowed to turn off for a maximum of
4 ms. After this time the PLLs will output a locked clock at a
preselected safe frequency. The safe frequency is either
based upon the power on reset default values or upon the
value stored in the safe frequency register. The safe frequency
register is accessible via SMBUS (Bytes 18 & 19). The clock
outputs must be stable at the correct safe frequency at least
2 ms before the deassertion of RESET_IN#.
CY28RS680-2
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