cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 17

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPUC(Free Running
CPUT(Free Running
CPUC(Stoppable)
CPUT(Stoppable)
CPU_STOP#
CPU_STP#
CPUC Internal
CPUT Internal
DOT96C
DOT96T
CPU_STP#
PD#
CPUT
CPUC
CPUT
CPUC
Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
Figure 6. CPU_STP# Assertion Waveform
Figure 7. CPU_STP# Deassertion Waveform
Tdrive_CPU_STP#,10 ns>200 mV
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
1.8 ms
CY28548
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