cy28159 Cypress Semiconductor Corporation., cy28159 Datasheet - Page 9

• Manufacturer Part Number: cy28159
• Description: Clock Generator For Serverworks Grand Champion Chipset Applications Semiconductor
• Manufacturer: Cypress Semiconductor Corporation.

AC Parameters
Notes:
Document #: 38-07118 Rev. **
10. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and at 20% and 80% for CPU[(0:7), (0:7)#] signals
11. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at crossing points for CPU clocks (see Figure 3).
12. This measurement is applicable with Spread ON or Spread OFF.
13. Probes are placed on the pins, and measurements are acquired at 2.4V (see Figure 3).
14. Probes are placed on the pins, and measurements are acquired at 0.4V. (seeFigure 3).
15. As this function is available through SEL(0,1), therefore, the time specified is guaranteed by design.
16. Determined as a fraction of 2*(Trp-Trn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
8.
9.
TPeriod
Tr/Tf
TSKEW1
TCJJ
Vover
Vunder
Vcrossover CPU(0:7), to CPU(0:7)# Crossover Point
Tduty
Tperiod
THIGH
TLOW
Tr/Tf
TCCJ
Tduty
Tperiod
Tr/Tf
TCCj
Tduty
TDC
Tperiod
Tr/Tf
TCCJ
Zout
tpZL, tpZH
tpLZ, tpZH
tstable
Symbol
This parameter is measured at the crossing points of the differential signals, and acquired as an average over 1 s duration, with a crystal center frequency of
14.31818 MHz.
All outputs loaded as per Table 3, see Figure 2.
(see Figure 3).
CPU(0:7), (0:7)#) Period
CPU[(0:7), (0:7)#] Rise and Fall Times
Skew from Any CPU Pair to Any CPU Pair
CPU[(0:7), (0:7)#] Cycle to Cycle Jitter
CPU[(0:7), (0:7)#] Overshoot
CPU[(0:7), (0:7)#] Undershoot
Duty Cycle
3V33 Period
3V33 High Time
3V33 Low Time
3V33 Rise and Fall Times
3V33 Cycle to Cycle Jitter
Duty Cycle
REF Period
REF Rise and Fall Times
REF Cycle to Cycle Jitter
Duty Cycle
48MHz(0,1) Duty Cycle
48MHz(0.1) Period
48MHz(0,1) Rise and Fall Times
48MHz(0,1) Cycle to Cycle Jitter
48MHz Buffer Output Impedance
Output Enable Delay (all outputs)
Output Disable Delay (all outputs)
All Clock Stabilization from Power-up
(V
DD
= V
Description
DDA
= 3.3V ±5%, T
A
= 0°C to +70°C)
33MHz
48MHz
45%Voh
69.8412
20.8299
REF
CPU
Min.
7.35
15.0
5.25
5.05
175
0.5
1.0
1.0
1.0
1.0
133 MHz Host
45
45
45
45
20
Voh + 0.2
55%Voh
20.8333
Max.
1000
7.65
–0.2
16.0
71.0
10.0
10.0
700
100
150
300
500
2.0
4.0
4.0
55
55
55
55
3
45%Voh
69.8413
20.8299
Min.
9.85
15.0
5.25
5.05
175
100 MHz Host
0.5
1.0
1.0
1.0
1.0
45
45
45
45
20
-
Voh + 0.2
55%Voh
20.8333
Max.
1000
10.2
15.2
71.0
10.0
10.0
-0.2
700
100
150
300
500
2.0
4.0
4.0
55
55
55
55
3
Unit
nS
nS
pS
ms
ns
ps
ps
ps
ns
ns
ns
ns
ps
ns
ps
ps
ns
ns
%
%
%
%
V
V
V
CY28159
Page 9 of 13
9,11,12
9,11,12
9,11,12
8, 9,11
Notes
9,10
9,16
9,16
9,13
9,14
9,10
9,10
9,10
9,11
9,11
9,11
9,11
9,11
9,11
9,11
9,11
9,11
9,11
15
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