cy28159 Cypress Semiconductor Corporation., cy28159 Datasheet

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cy28159

Manufacturer Part Number
cy28159
Description
Clock Generator For Serverworks Grand Champion Chipset Applications Semiconductor
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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59
Features
Table 1. Frequency Selection
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07118 Rev. **
• Eight differential CPU clock outputs
• One PCI output
• One 14.31818-MHz reference clock
• Two 48-MHz clocks
SEL 100/133
Clock Generator for Serverworks Grand Champion Chipset Applications
Block Diagram
SEL100/133
MultSel(0:1)
0
0
0
0
1
1
1
1
SSCG#
XOUT
I_Ref
PD#
XIN
OSC
S0
0
0
1
1
0
0
1
1
VCO
S(0,1)
S1
0
1
0
1
0
1
0
1
Control
I
CPU(0:7), CPU#(0:7)
VDDI
VSSI
133.3MHz
133.3MHz
VDDL
VSSL
100 MHz
100 MHz
100 MHz
200MHz
Hi-Z
N/A
REF
CPU (0:7)
CPU (0:7)#
48M(0,1)/S(0,1)
3V33
3901 North First Street
33.3MHz
33.3MHz
33.3MHz
33.3MHz
33.3MHz
Disable
3V33
• All outputs compliant with Intel
• External resistor for current reference
• Selection logic for differential swing control, test mode,
• 48-pin SSOP and TSSOP packages
Hi-Z
N/A
Hi-Z, power-down and spread spectrum
Pin Configuration
48M0/S0
48M1/S1
SSCG#
CPU0#
CPU1#
CPU2#
CPU3#
XOUT
CPU0
CPU1
CPU2
CPU3
3V33
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
REF
VSS
XIN
San Jose
48M(0,1)
48 MHz
48 MHz
48 MHz
Disable
Disable
Disable
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Hi-Z
N/A
CA 95134
Test Mode(recommended)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Revised January 14, 2002
Test Mode (optional)
®
Normal Operation
Hi-Z all outputs
specifications
Reserved
o7ptional
Optional
Optional
SEL100/133
VSS
VDDA
VSSA
PD#
VDD
CPU4
CPU4#
VSS
CPU5
CPU5#
VDD
CPU6
CPU6#
VSS
CPU7
CPU7#
VDD
MULT0
MULT1
VSS
VSSA
IREF
VDDA
Notes
CY28159
408-943-2600

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cy28159 Summary of contents

Page 1

... SSCG VSS 21 28 XIN 22 27 XOUT 23 26 VDD 24 25 • San Jose • CA 95134 Revised January 14, 2002 CY28159 Notes SEL100/133 VSS VDDA VSSA PD# VDD CPU4 CPU4# VSS CPU5 CPU5# VDD CPU6 CPU6# VSS CPU7 CPU7# VDD MULT0 MULT1 VSS ...

Page 2

... CPU clock output pairs. Each pin has a 250-k internal Pull-up. See Table 5 for current and resistor values. P 3.3V power supply pins. P 3.3V power supply pins for common supply to the core. P Ground pins for common supply to the core. P Ground pins. CY28159 Description Page ...

Page 3

... Table 3. Group Limits and Parameters (Applicable to all settings: Sel133/100#=x) Comments Output Name CPU[(0:7)#] REF 3V33 T PCB 2pF T PCB 2pF Figure 1. 0.7V Test Load Termination Output Under Test Probe C LOAD Figure 2. Lumped Load Termination CY28159 Max Load See Figure Measurement Point Measurement Point Page ...

Page 4

... Document #: 38-07118 Rev Figure 3. 3.3V Measurement Points CY28159 - Page ...

Page 5

... Note 475 1%, Iref = 2. 475 1%,Iref = 2. 475 1%,Iref = 2. 475 1%,Iref = 2. 475 1%,Iref = 2. 475 1%,Iref = 2. 475 1%,Iref = 2. 475 1%,Iref = 2. CY28159 F Max(MHz) Spread (%) 100 –0.5% 133 –0.5% 200 –0.5% Voh@Z, Iref = Output Current 2.32 mA Ioh = 5*Iref ...

Page 6

... Minimum 3000 Ohms (recommended) Unspecified N/A The various output current configurations are shown in the host swing select functions table. For all configurations, the deviation from the expected output current is ±7% as shown in the table current accuracy. CY28159 1.2V Vout Maximum N/A Unspecified 1.2 Volt Page ...

Page 7

... OH DDmin (1.56V) OH DDmin (1.56V) OL DDmin 3.3V ± 0.4V–2.4V 3.3V ± 2.4V–0.4V CY28159 Load Min. Nominal test load for –7% Inom +7% Inom given configuration Nominal test load for –12% +12% Inom given configuration Inom Min. Typ. Max. –12 –53 –27 – ...

Page 8

... Measured from Pin to Ground. From stable 3.3V power supply and V should be constrained to the IN OUT or V )< OUT Min. Typ. 2.0 [5] – 200 250 CY28159 Max. Unit 0.8 Vdc Vdc – 200 ...

Page 9

... Voh + 0.2 –0.2 45%Voh 55%Voh 45 55 33MHz 15.0 16.0 5.25 5.05 0.5 2.0 300 45 55 REF 69.8412 71.0 1.0 4.0 1000 45 55 48MHz 45 55 20.8299 20.8333 1.0 4.0 500 20 1.0 10.0 1.0 10.0 3 CY28159 100 MHz Host Unit Notes Min. Max. 9.85 10.2 ns 9,11 175 700 ps 9,10 100 ps 9,11,12 150 ps 9,11,12 Voh + 0.2 V 9,16 -0.2 V 9,16 45%Voh 55%Voh 9,11 15.0 15.2 ns 9,11 5.25 ns 9,13 5.05 ...

Page 10

... & 0.005 µF V =VIA to respective supply plane layer CY28159 FB * VDDQ3A 10 F 0.005 ...

Page 11

... Document #: 38-07118 Rev. ** Package Type 48-Pin SSOP 48-Pin SSOP - Tape and Reel 48-Pin TSSOP 48-Pin TSSOP - Tape and Reel 48-Lead Shrunk Small Outline Package O48 CY28159 Product Flow Commercial Commercial Commercial Commercial 51-85061-*C ...

Page 12

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. (continued) CY28159 51-85059-B Page ...

Page 13

... Document Title: CY28159 Clock Generator for Serverworks Grand Champion Chipset Applications Document Number: 38-07118 Issue REV. ECN NO. Date ** 111426 01/22/02 Document #: 38-07118 Rev. ** Orig. of Change DMG New data sheet CY28159 Description of Change Page ...

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