cy25561 Cypress Semiconductor Corporation., cy25561 Datasheet - Page 3

• Manufacturer Part Number: cy25561
• Description: Spread Spectrum Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07242 Rev. *B
Tri-level Logic
With binary logic, four states can be programmed with two
control lines, whereas tri-level logic can program nine logic
states using two control lines. Tri-level logic in the CY25561 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0”. Pins 6 and 7 of the CY25561
recognize a logic state by the voltage applied to the respective
pin. These states are defined as “0” (Low), “M” (Middle), and
SSCG Theory of Operation
The CY25561 is a PLL-type clock generator using a propri-
etary Cypress design. By precisely controlling the bandwidth
of the output clock, the CY25561 becomes a low-EMI clock
generator. The theory and detailed operation of the CY25561
is discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50-duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e.; third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
and odd harmonics by increasing the bandwidth of the funda-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse-
quently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI have been to use shielding, filtering,
multilayer PCBs, etc. The CY25561 uses the approach of
reducing the peak energy in the clock by increasing the clock
bandwidth, and lowering the Q.
S1 = "0" (GND)
SSCC = "1"
S0 = "M" (N/C)
CY25561
7
6
5
S0
VDD
S1
Figure 1. Tri-level Logic Examples
S1 = "0" (GND)
SSCC = "1"
CY25561
S0 = "1"
5
7
6
“1” (One). Each of these states has a defined voltage range
that is interpreted by the CY25561 as a “0,” “M,” or “1” logic
state. Refer to Table 2 for voltage ranges for each logic state.
The CY25561 has two equal value resistors connected inter-
nally to pin 6 and pin 7 that produce the default “M” state. Pins
6 and/or 7 can be tied directly to ground or V
Logic “0” or “1” state, respectively. See examples below.
SSCG
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
both peak and cycle to cycle. The CY25561 takes a narrow
band digital reference clock in the range of 50–166 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand
what happens to a clock when SSCG is applied, consider a
65-MHz clock with a 50% duty cycle. From a 65-MHz clock we
know the following.
If this clock is applied to the Xin/CLK pin of the CY25561, the
output clock at pin 4 (SSCLK) will be sweeping back and forth
between two frequencies. These two frequencies, F1 and F2,
are used to calculate to total amount of spread or bandwidth
applied to the reference clock at pin 1. As the clock is making
the transition from F1 to F2, the amount of time and sweep
waveform play a very important role in the amount of EMI
reduction realized from an SSCG clock.
The modulation domain analyzer is used to visualize the
sweep waveform and sweep period. Figure 3 shows the
modulation profile of a 65 MHz SSCG clock. Notice that the
actual sweep waveform is not a simple sine or sawtooth
waveform. Figure 3 also shows a scan of the same SSCG
clock using a spectrum analyzer. In this scan you can see a
6.48-dB reduction in the peak RF energy when using the
SSCG clock.
Clock Frequency = fc = 65MHz
Clock Period = Tc =1/65 MHz = 15.4 ns
S0
VDD
S1
VDD
S0 = "1"
S1 = "1"
SSCC = "1"
CY25561
50 %
Tc = 15.4 ns
7
6
5
DD
CY25561
50 %
to program a
S1
Page 3 of 8
S0
VDD
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