cy25561 Cypress Semiconductor Corporation., cy25561 Datasheet - Page 2

• Manufacturer Part Number: cy25561
• Description: Spread Spectrum Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07242 Rev. *B
Pin Description
General Description
The Cypress CY25561 is a Spread Spectrum Clock Generator
(SSCG) IC used for the purpose of reducing electromagnetic
Interference (EMI) found in today’s high-speed digital
electronic systems.
The CY25561 uses a Cypress proprietary phase-locked loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies
of Clock (SSCLK) is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading the system performance.
The CY25561 is a very simple and versatile device to use. The
frequency and spread % range is selected by programming S0
and S1 digital inputs. These inputs use three (3) logic states
including High (H), Low (L), and Middle (M) logic levels to
Table 1. Frequency and Spread %Selection (Center Spread)
Pin
1
2
3
4
5
6
7
8
Frequ en cy
Frequ en cy
100 - 1 20
130 - 1 40
140 - 1 50
150 - 1 66
120 -130
80 - 100
50 - 60
60 - 70
70 - 80
(M H z)
(M H z)
Inp ut
Inp ut
Xin/CLK
SSCLK
SSCC
Name
GND
VDD
Xout
S1
S0
S1 =M
S0 =M
S0 =M
S1=1
(% )
(% )
4.3
4.0
3.8
3.5
3.0
2.7
2.6
2.6
2.5
Type
O
O
P
P
I
I
I
I
100–166 M H z (H ig h R an ge)
50–100 M H z (L ow R an ge)
Clock or crystal connection input. Refer to Table 1 for input frequency range selection.
Positive power supply.
Power supply ground.
Modulated clock output.
Spread Spectrum clock control (enable/disable) function. SSCG function is enabled
when input is high and disabled when input is low. This pin is pulled high internally.
Tri-level logic input control pin used to select frequency and bandwidth.
Frequency/Bandwidth selection and Tri-level logic programming. See Figure 1. Pin 6 has
internal resistor divider network to V
Tri-level logic input control pin used to select Frequency and Bandwidth.
Frequency/Bandwidth selection and Tri-level logic programming. See Figure 1. Pin 7 has
internal resistor divider network to V
Oscillator output pin connected to crystal. Leave this pin unconnected If an external
clock drives Xin/CLK.
S1 =M
S0 =0
S1 =0
S0 =1
(% )
(% )
3.9
3.6
3.4
3.1
2.4
2.1
2.0
2.0
1.8
S1 =1
S0 =0
S1 =1
S0 =1
(% )
(% )
3.3
3.1
2.9
2.7
1.5
1.4
1.3
1.3
1.2
select one of the nine available Spread % ranges. Refer to
Table 1 for programming details.
The CY25561 is intended for use with applications with a
reference frequency in the range of 50 to 166 MHz.
A wide range of digitally selectable spread percentages is
made possible by using Tri-level (High, Low, and Middle) logic
at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread Spectrum Clock Control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
The CY25561 is available in an eight-pin SOIC package with
a 0°C-to-70°C operating temperature range.
Refer to the CY25560 data sheet for operation at frequencies
from 25 to 100 MHz.
DD
DD
S1 =M
S1 =0
S0 =0
S0 =1
(% )
(% )
2.9
2.6
2.5
2.2
1.3
1.1
1.1
1.1
1.0
Description
and V
and V
SS
SS
. Refer to Block Diagram on page 1.
. Refer to Block Diagram on page 1.
S 0=M
S1 =0
(% )
2.7
2.5
2.4
2.1
S elect th e
F req u enc y and
C en ter S p read %
d esired and th en
set S 1, S 0 as
in dicated .
S elect th e
F req u enc y and
C en ter S p read %
d esired and th en
set S 1, S 0 as
in dicated .
CY25561
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