cy24292 Cypress Semiconductor Corporation., cy24292 Datasheet
cy24292
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cy24292 Summary of contents
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... Cypress Semiconductor Corporation Document Number: 001-46142 Rev. *C Four Outputs PCI-Express Clock Generator Functional Description CY24292 is a clock generator device intended for PCI-Express applications. The device includes: four 100 MHz differential clocks with HCSL or LVDS compatible outputs for PCI-Express, and one single-ended 25 MHz output. ...
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... Recommended Operation Conditions .............................11 DC Electrical Characteristics ...........................................11 AC Electrical Characteristics ...........................................12 Test and Measurement Setup ...........................................13 Single-ended Signals ................................................... 13 Differential Signals ....................................................... 13 Ordering Information .........................................................14 Package Dimensions .........................................................14 Document History Page ....................................................15 Sales, Solutions, and Legal Information .........................16 Worldwide Sales and Design Support.......................... 16 Products ....................................................................... 16 PSoC Solutions ............................................................ 16 CY24292 Page [+] Feedback ...
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... Pinout Figure 1. Pin Diagram - CY24292 32-Pin Device PCIE1P PCIE1N GND IREF PCIE2N PCIE2P GND VDD Table 1. Pin Definitions - CY24292 32-Pin Device Pin Number Pin Name Pin Type 1 PCIE1P Output 2 PCIE1N Output 3 GND Power 4 IREF Output 5 PCIE2N Output 6 PCIE2P Output 7 GND Power ...
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... Table 1. Pin Definitions - CY24292 32-Pin Device (continued) Pin Number Pin Name Pin Type 20 PD_RESET# Input 21 VDD Power 22 XIN/EXCLKIN Input 23 XOUT Output 24 VDD Power 25M Output 27 GND Power 28 VDD Power 29 GND Power 30 VDD Power 31 GND Power 32 VDD Power SMBus Serial Data Interface A two-signal serial interface is provided to enhance the flexibility and function of the clock synthesizer ...
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... Command code – 8 bits ‘1xxxxxxx’ stands for byte operation, of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not acknowledge 39 Stop CY24292 Page [+] Feedback ...
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... MHz PCI-Express OE for 100 MHz PCI-Express output PCIE1 output PCIE1 100 MHz PCI-Express OE for 100 MHz PCI-Express output PCIE0 output PCIE0 Not applicable Not used Outputs Affected Not applicable Not used CY24292 Description Notes 1 = -0.5% down 1 = enabled 0 = disabled 1 = enabled Description Notes Description Notes ...
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... Not applicable Vendor ID bit 1 Not applicable Vendor ID bit 0 Outputs Affected Not applicable Not used 0 Disabled, Hi-Z. 25M has weak pull-down. 1 Disabled, Hi-Z. 25M has weak pull-down. 0 Disabled, Hi-Z. 25M has weak pull-down. 1 CY24292 Description Notes Description Notes All Clock Outputs Enabled Page [+] Feedback ...
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... Application Information Crystal Recommendations The CY24292 requires a parallel resonance crystal. Substituting a series resonance crystal causes the CY24292 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300 ppm frequency shift between the series and parallel crystals due to incorrect loading. ...
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... Decoupling Capacitors Decoupling capacitors of 0.01 µF must be connected between VDD and GND as close to the device as possible. Do not share ground vias between components. Route power from power source through the capacitor pad, and then into the CY24292 pin. Dimension or Value 0.5 max 0.2 max ...
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... Dimension or Value 0.5 max 0.2 max 0.2 max 100 150 33 49.9 [2] Dimension or Value 1 Figure 4. LVDS Device Routing CY24292 Unit inch inch inch Ω Ω Ω Ω Unit inch inch R P LVDS Device Input Page [+] Feedback ...
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... R = 49.9 Ω Ω 49.9 Ω 4mA OL = 6*I OH REF No load, PD_RESET# pin = 1 Full load, PD_RESET# pin = 1 PD_RESET# pin = 0 All input pins PD_RESET CY24292 Min Max Unit –0.5 4.6 V –0 –65 150 °C – 125 °C 2000 – V V-0 at 1/8 in. ...
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... See notes 5 and 13 Measured at V point CROSS See note 14 Measured at V point CROSS [14] See note 14 PD_RESET# going high to 99% of final frequency Measured from 90% of the applied power supply level CY24292 = 475 Ω REF Min Typ Max Unit – 25 – MHz – 0 – ...
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... Single-ended Signals Figure 5. Test Load Configuration for Single-ended Output Signal Differential Signals Figure 6. Test Load Configuration for Differential Output Signal PCIEP PCIEN Document Number: 001-46142 Rev. *C 453 Ohm CLoad 33 Ohm 33 Ohm 475 Ohm CY24292 50 Ohm CLoad 50 Ohm CLoad 50 Ohm Page [+] Feedback ...
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... QFN tape and reel Package Dimensions Document Number: 001-46142 Rev. *C Type Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, -40°C to 85°C Industrial, -40°C to 85°C Figure 7. 32-Pin QFN Package CY24292 Production Flow 001-42168 *D Page [+] Feedback ...
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... Document History Page Document Title: CY24292 Four Outputs PCI-Express Clock Generator Document Number: 001-46142 Rev. ECN No. Orig. of Change ** 2490167 PYG/DPF/AESA *A 2507681 DPF/AESA *B 2811340 CXQ *C 2901711 KVM Document Number: 001-46142 Rev. *C Submission Description of Change Date See ECN New Data Sheet. 05/23/2008 Changed pinout based on PCIE_Bonding_Rev G. ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-46142 Rev. *C All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised May 14, 2010 CY24292 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...