cy24c01 Cypress Semiconductor Corporation., cy24c01 Datasheet - Page 4

• Manufacturer Part Number: cy24c01
• Description: 1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, And 16 Kbit X8 Two Wire I2c Serial Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Device Addressing
The CY24C01/02/04/08/16 EEPROM requires an 8-bit device
address word after a start condition, to enable the chip for a read
or write operation (refer to
The device address word consists of a mandatory one, zero
sequence for the first four most significant bits as shown in
Table 3
The next three bits are the A2, A1, and A0 device address bits
for CY24C01 and CY24C02. These three bits must compare to
their corresponding hard wired input pins.
CY24C04 uses only the A2 and A1 device address bits. The third
bit is a memory page address bit. The two device address bits
must compare to their corresponding hard wired input pins. The
A0 pin is no connect.
CY24C08 only uses the A2 device address bit with the next 2 bits
being for memory page addressing. The A2 bit must compare to
its corresponding hard wired input pin. The A1 and A0 pins are
no connect.
CY24C16 does not use any device address bits and the 3 bits
are used for memory page addressing. The page addressing bits
on the 4K, 8K, and 16K devices must be considered the most
significant bits of the data word address which follows. The A0,
A1, and A2 pins are no connect.
The eighth bit of the device address is the read or write operation
select bit. A read operation is initiated if this bit is high and a write
operation is initiated if this bit is low.
When the device address is compared, the EEPROM outputs a
zero. If a compare is not made, the chip returns to the standby
state.
Document #: 001-15632 Rev. *C
on page 5. This is common to all the EEPROM devices.
Data Out
Data In
SCL
Table 3
Start
on page 5).
1
Figure 3. Acknowledge Timing
Write Operations
Byte Write
A write operation requires an 8-bit data word address following
the device address word and acknowledgment. On receipt of this
address, the EEPROM responds with a zero and then clocks in
the first 8-bit data word. Following the receipt of the 8-bit data
word, the EEPROM outputs a zero. The addressing device, such
as a microcontroller, must terminate the write sequence with a
stop condition. At this time the EEPROM enters an internally
timed write cycle, t
disabled during this write cycle and the EEPROM does not
respond until the write is complete (see
Page Write
The CY24C01/02/04/08/16/CY24C08/CY24C16 devices are
capable of 16-byte page writes.
A page write is initiated in the same way as a byte write, but the
microcontroller does not send a stop condition after the first data
word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up
to 15 more data words. The EEPROM responds with a zero after
each data word is received. The microcontroller must terminate
the page write sequence with a stop condition
(see
The lower four bits of the data word address are internally
incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the
memory page row location. When the internally generated word
address reaches the page boundary, the next byte is placed at
the beginning of the same page. If more than 16 data words are
transmitted to the EEPROM, the data word address rolls over
and the previous data is overwritten.
Acknowledge Polling
When the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling is initiated.
This involves sending a start condition followed by the device
address word. The read or write bit is representative of the
operation desired. After the internal write cycle is complete, the
EEPROM responds with a zero, enabling the read or write
sequence to continue.
Figure 5
on page 6).
WR
8
, to the nonvolatile memory. All inputs are
CY24C01/02/04/08/16
Acknowledge
Figure 4
9
on page 6).
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