cy29772 Cypress Semiconductor Corporation., cy29772 Datasheet - Page 8

• Manufacturer Part Number: cy29772
• Description: 2.5v Or 3.3v, 200-mhz, 12-output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07572 Rev. *A
AC Parameters
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other the SYNC output provides a
signal for system synchronization. The CY29772 monitors the
relationship between the QA and the QC output clocks. It
provides a low going pulse, one period in duration, one period
prior to the coincident rising edges of the QA and QC outputs.
tsk(B)
t
t
BW
t
t
t
t
PLZ, HZ
PZL, ZH
JIT(CC)
JIT(PER)
JIT(φ)
LOCK
Parameter
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
PLL Closed-Loop Bandwidth
(–3 dB)
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
(V
DD
= 3.3V ± 5%, T
Description
A
= –40°C to +85°C) (continued)
Skew within Bank C
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
Same frequency (125 MHz)
RMS (1σ)
Same frequency
Multiple frequencies
Same frequency (125 MHz)
RMS (1σ)
Same frequency
Multiple frequencies
I/O same VDD
Condition
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. Figure 1 illus-
trates various waveforms for the SYNC output. Note that the
SYNC output is defined for all possible combinations of the QA
and QC outputs even though under some relationships the
lower frequency clock could be used as a synchronizing
signal.
[6]
Min.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.3–2.0
0.7–1.3
0.9–1.3
0.6–1.1
0.6–0.9
0.6–0.9
0.–0.6
Typ.
45
–
–
–
–
7
–
–
6
–
–
–
Max.
150
325
100
375
225
150
30
30
75
8
8
–
–
–
–
–
–
–
1
CY29772
Page 8 of 12
MHz
Unit
ms
ps
ns
ns
ps
ps
ps
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