cy29772 Cypress Semiconductor Corporation., cy29772 Datasheet
cy29772
Available stocks
Related parts for cy29772
cy29772 Summary of contents
Page 1
... The CY29772 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock-distribution applications. The CY29772 features one on-chip crystal oscillator and two LVCMOS reference clock inputs and provides 12 outputs parti- tioned in three banks of four outputs each. Each bank divides the VCO output per SEL(A:C) settings, see Functional Table ...
Page 2
... Power supply for bank A output clocks. VDD 2.5V or 3.3V Power supply for bank B output clocks. VDD 2.5V or 3.3V Power supply for bank C output clocks. VDD 2.5V or 3.3V Power supply for PLL. VDD 2.5V or 3.3V Power supply for core and inputs. Ground Analog Ground. Ground Common Ground. CY29772 [2,3] [2,3] [2,3] [2,3] [2,3] Page [+] Feedback ...
Page 3
... QB(0:3) ÷8 ÷12 ÷16 ÷20 ÷4 ÷6 ÷8 ÷10 CY29772 Input Frequency Range (AVDD = 2.5V) 6.25 MHz to 11.8 MHz 1 SELC0 QC(0:3) ÷4 0 ÷8 1 ÷ ³16 ÷2 0 ÷4 1 ÷6 0 ÷8 1 Page [+] Feedback ...
Page 4
... Document #: 38-07572 Rev. *A FB_OUT ÷8 0 ÷12 1 ÷16 0 ÷20 1 ÷16 0 ÷24 1 ÷32 0 ÷40 1 ÷4 0 ÷6 1 ÷8 0 ÷10 1 ÷8 0 ÷12 1 ÷16 0 ÷20 1 CY29772 Page [+] Feedback ...
Page 5
... – AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz . Alternatively, each output drives up to two 50Ω series-terminated transmis- TT CY29772 Min. Max. Unit –0.3 5.5 V 2.375 3.465 V –0 0 –0 0 ÷ 2 – ...
Page 6
... Skew within Bank B Skew within Bank C ÷4 Feedback ÷6 Feedback ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback . Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed TT CY29772 Min. Typ. Max. Unit – 200 380 MHz – 10 ...
Page 7
... Output ÷12 Output ÷16 Output ÷20 Output ÷24 Output f < 100 MHz MAX f > 100 MHz MAX 0.55V to 2.4V TCLK to FB_IN, same VDD Skew within Bank A Skew within Bank B CY29772 [6] Min. Typ. Max. Unit – – – 150 – – ...
Page 8
... SYNC Output In situations where output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The CY29772 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs ...
Page 9
... QA QC SYNC Power Management The individual output enable/freeze control of the CY29772 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks ...
Page 10
... The crystal’s rated load ohm ohm T VTT t(φ) VDD VDD GND 100% Figure 5. Output Duty Cycle (DC) CY29772 Min. Typ. Max. Unit – – ±1100 PPM – – ± 100 PPM – – 5 PPM/Yr – ...
Page 11
... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. t SK(O) Figure 6. Output-to-Output Skew, t sk(O) Package Type CY29772 VDD VDD/2 GND VDD VDD/2 GND Product Flow Industrial, – ...
Page 12
... Document History Page Document Title:CY29772 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Document Number: 38-07572 REV. ECN No. Issue Date ** 129007 09/03/03 *A 395853 See ECN Document #: 38-07572 Rev. *A Orig. of Change Description of Change RGL New Data Sheet Added Lead-free devices RGL Added Jitter typical specs in the features section ...